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-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl15
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl35
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl23
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl13
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl26
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl16
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl16
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl15
8 files changed, 159 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl
new file mode 100644
index 0000000..88b3d13
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/constants/simple-string-constant.vhdl
@@ -0,0 +1,15 @@
+entity test is
+end test;
+
+architecture only of test is
+begin -- only
+ doit: process
+ constant string_constant : string := "init";
+ begin -- process
+ assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
+ assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
+ assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
+ assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
+ wait;
+ end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl
new file mode 100644
index 0000000..1e479aa
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl
@@ -0,0 +1,35 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+ signal sig : integer := 0;
+begin -- only
+ assign: process
+ begin -- process p
+ sig <= 1;
+ wait;
+ end process assign;
+
+ check1: process
+ begin -- process check1
+ wait for 1 fs;
+ assert sig = 1 report "TEST FAILED" severity FAILURE;
+ wait;
+ end process check1;
+
+ check2: process
+ begin -- process check1
+ wait for 1 fs;
+ assert sig = 1 report "TEST FAILED" severity FAILURE;
+ wait;
+ end process check2;
+
+ check3: process
+ begin -- process check1
+ wait for 2 fs;
+ report "TEST PASSED" severity NOTE;
+ wait;
+ end process check3;
+
+
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl
new file mode 100644
index 0000000..3efa37b
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl
@@ -0,0 +1,23 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+ signal sig : integer := 0;
+begin -- only
+ p: process
+ begin -- process p
+ sig <= 1;
+ wait for 1 fs;
+ assert sig = 1 report "TEST FAILED" severity FAILURE;
+ report "TEST PASSED" severity NOTE;
+ wait;
+ end process p;
+
+ r: process (sig)
+ begin -- process r
+ if sig'event then
+ report "Event on sig, new value = " & integer'image( sig );
+ end if;
+ end process r;
+
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl
new file mode 100644
index 0000000..91e45eb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl
@@ -0,0 +1,13 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+ signal sig : integer := 0;
+begin -- only
+ p: process
+ begin -- process p
+ assert sig = 0 report "TEST FAILED" severity FAILURE;
+ report "TEST PASSED" severity NOTE;
+ wait;
+ end process p;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl
new file mode 100644
index 0000000..1f7e65f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/integer-variable-persist-across-activations.vhdl
@@ -0,0 +1,26 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+ signal clock : bit;
+begin -- only
+ process (clock)
+ variable x : integer := 0;
+ variable l : line;
+ begin -- process
+ write( l, string'( "x = " ) );
+ write( l, x );
+ writeline( output, l );
+ x := x + 1;
+ end process;
+
+ process
+ begin -- process
+ clock <= '1' after 1 ns,
+ '0' after 2 ns,
+ '1' after 3 ns;
+ wait;
+ end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl
new file mode 100644
index 0000000..e324a39
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-enumeration-assign.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin -- only
+ process
+ variable x : boolean := false;
+ begin -- process
+ x := true;
+ assert x = true report "TEST FAILED - x does not equal true" severity failure;
+ assert x /= true report "TEST PASSED" severity note;
+ wait;
+ end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl
new file mode 100644
index 0000000..265cadb
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-assign.vhdl
@@ -0,0 +1,16 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin -- only
+ process
+ variable x : integer := 0;
+ begin -- process
+ x := 1;
+ assert x = 1 report "TEST FAILED - x does not equal 1" severity failure;
+ assert x /= 1 report "TEST PASSED" severity note;
+ wait;
+ end process;
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl
new file mode 100644
index 0000000..fc2ded3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/variable/simple-integer-initialize.vhdl
@@ -0,0 +1,15 @@
+entity foo is
+end foo;
+
+use std.textio.all;
+
+architecture only of foo is
+begin -- only
+ process
+ variable x : integer := 0;
+ begin -- process
+ assert x = 0 report "TEST FAILED - x does not equal 1" severity failure;
+ report "TEST PASSED" severity note;
+ wait;
+ end process;
+end only;