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diff --git a/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1276.vhd b/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1276.vhd
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+
+-- Copyright (C) 2001 Bill Billowitch.
+
+-- Some of the work to develop this test suite was done with Air Force
+-- support.  The Air Force and Bill Billowitch assume no
+-- responsibilities for this software.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: tc1276.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
+-- $Revision: 1.2 $
+--
+-- ---------------------------------------------------------------------
+
+ENTITY c08s04b00x00p04n01i01276ent IS
+END c08s04b00x00p04n01i01276ent;
+
+ARCHITECTURE c08s04b00x00p04n01i01276arch OF c08s04b00x00p04n01i01276ent IS
+  signal S1,S2,S3 : integer ;
+BEGIN
+  TESTING: PROCESS
+  BEGIN
+    S1 and S2   <= S3;
+    assert FALSE
+      report "***FAILED TEST: c08s04b00x00p04n01i01276 - Logical expressions are not allowed on the left-hand side of a signal assignment." 
+      severity ERROR;
+    wait;
+  END PROCESS TESTING;
+
+END c08s04b00x00p04n01i01276arch;