5 files changed, 49 insertions, 1 deletions
diff --git a/testsuite/gna/ticket37/genbool.vhdl b/testsuite/gna/ticket37/genbool.vhdl
new file mode 100644
index 0000000..438da77
--- /dev/null
+++ b/testsuite/gna/ticket37/genbool.vhdl
@@ -0,0 +1,8 @@
+entity genbool is
+  generic (val : boolean := False);
+end genbool;
+
+architecture behav of genbool is
+begin
+  assert val severity failure;
+end behav;
diff --git a/testsuite/gna/ticket37/genchar.vhdl b/testsuite/gna/ticket37/genchar.vhdl
new file mode 100644
index 0000000..fa14919
--- /dev/null
+++ b/testsuite/gna/ticket37/genchar.vhdl
@@ -0,0 +1,8 @@
+entity genchar is
+  generic (val : character := CR);
+end genchar;
+
+architecture behav of genchar is
+begin
+  assert val = Ack or val = 'A' or val = 'z' severity failure;
+end behav;
diff --git a/testsuite/gna/ticket37/genint.vhdl b/testsuite/gna/ticket37/genint.vhdl
index 742d109..51ac559 100644
--- a/testsuite/gna/ticket37/genint.vhdl
+++ b/testsuite/gna/ticket37/genint.vhdl
@@ -12,4 +12,3 @@ architecture behav of genint is
 begin
   assert val = -159 or val = 9 severity failure;
 end behav;
-  
diff --git a/testsuite/gna/ticket37/genlogic.vhdl b/testsuite/gna/ticket37/genlogic.vhdl
new file mode 100644
index 0000000..b64d21f
--- /dev/null
+++ b/testsuite/gna/ticket37/genlogic.vhdl
@@ -0,0 +1,11 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity genlogic is
+  generic (val : std_logic := '0');
+end genlogic;
+
+architecture behav of genlogic is
+begin
+  assert val = '1' or val = 'H' severity failure;
+end behav;
diff --git a/testsuite/gna/ticket37/testsuite.sh b/testsuite/gna/ticket37/testsuite.sh
index 0bbd207..f662f71 100755
--- a/testsuite/gna/ticket37/testsuite.sh
+++ b/testsuite/gna/ticket37/testsuite.sh
@@ -15,6 +15,28 @@ simulate genint -gVal=-159
 
 simulate_failure genint -gval=200
 
+analyze genchar.vhdl
+elab_simulate_failure genchar
+
+simulate genchar -gVAL=ack
+simulate genchar -gVAL="'A'"
+simulate genchar -gVAL="'z'"
+simulate_failure genchar -gVAL="'0'"
+simulate_failure genchar -gVAL=A
+
+analyze genbool.vhdl
+elab_simulate_failure genbool
+
+simulate genbool -gval=true
+simulate genbool -gval=" True"
+
+analyze genlogic.vhdl
+elab_simulate_failure genlogic
+
+simulate genlogic -gvaL="'1'"
+simulate genlogic -gvaL="'H'"
+simulate_failure genlogic -gvaL="'L'"
+
 clean
 
 echo "Test successful"