1 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/gna/perf02/add_142.vhd b/testsuite/gna/perf02/add_142.vhd
new file mode 100644
index 0000000..7898b11
--- /dev/null
+++ b/testsuite/gna/perf02/add_142.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_142 is
+	port (
+		output : out std_logic_vector(63 downto 0);
+		in_a : in  std_logic_vector(63 downto 0);
+		in_b : in  std_logic_vector(63 downto 0)
+	);
+end add_142;
+
+architecture augh of add_142 is
+
+	signal carry_inA : std_logic_vector(65 downto 0);
+	signal carry_inB : std_logic_vector(65 downto 0);
+	signal carry_res : std_logic_vector(65 downto 0);
+
+begin
+
+	-- To handle the CI input, the operation is '1' + CI
+	-- If CI is not present, the operation is '1' + '0'
+	carry_inA <= '0' & in_a & '1';
+	carry_inB <= '0' & in_b & '0';
+	-- Compute the result
+	carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+	-- Set the outputs
+	output <= carry_res(64 downto 1);
+
+end architecture;