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-rw-r--r--testsuite/gna/issue9/repro.vhdl8
1 files changed, 8 insertions, 0 deletions
diff --git a/testsuite/gna/issue9/repro.vhdl b/testsuite/gna/issue9/repro.vhdl
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+++ b/testsuite/gna/issue9/repro.vhdl
@@ -0,0 +1,8 @@
+entity tmp is end entity;
+architecture arch of tmp is
+ signal b : bit;
+begin
+ with true select b <=
+ '0' when false | true,
+ '1' when true;
+end architecture;