1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/gna/issue17/cond_assign_sig.vhdl b/testsuite/gna/issue17/cond_assign_sig.vhdl
new file mode 100644
index 0000000..ad8a0a4
--- /dev/null
+++ b/testsuite/gna/issue17/cond_assign_sig.vhdl
@@ -0,0 +1,28 @@
+library ieee ; 
+use ieee.std_logic_1164.all ; 
+use std.textio.all ; 
+
+entity cond_assign_sig is
+end entity cond_assign_sig ;
+
+architecture doit of cond_assign_sig is
+  signal Clk : std_logic := '0'  ; 
+  signal Y : std_logic ; 
+begin
+  Clk <= not Clk after 10 ns ; 
+  
+  process (Clk)
+  begin
+    Y <= 'H' when Clk = '1' else 'L' ;
+  end process ;
+
+--    Y <= 'H' when Clk = '1' else 'L' ;
+    
+  process
+  begin
+    wait for 500 ns ; 
+    std.env.stop ;
+  end process ; 
+end architecture doit ; 
+
+