diff options
Diffstat (limited to 'testsuite/gna/bug019/PoC/tb')
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/.gitignore | 2 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/config_tb.vhdl | 76 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/my_config_ML505.vhdl | 48 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/my_config_ML605.vhdl | 50 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/my_project.vhdl | 52 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/simulation.v08.vhdl | 363 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/simulation.v93.vhdl | 308 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/common/strings_tb.vhdl | 123 | ||||
| -rw-r--r-- | testsuite/gna/bug019/PoC/tb/io/uart/uart_rx_tb.vhdl | 141 |
9 files changed, 1163 insertions, 0 deletions
diff --git a/testsuite/gna/bug019/PoC/tb/.gitignore b/testsuite/gna/bug019/PoC/tb/.gitignore new file mode 100644 index 0000000..4095aa1 --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/.gitignore @@ -0,0 +1,2 @@ +*-obj93.cf +*_tb diff --git a/testsuite/gna/bug019/PoC/tb/common/config_tb.vhdl b/testsuite/gna/bug019/PoC/tb/common/config_tb.vhdl new file mode 100644 index 0000000..1c0ab59 --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/config_tb.vhdl @@ -0,0 +1,76 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Testbench: Tests global constants, functions and settings +-- +-- Authors: Thomas B. Preusser +-- Patrick Lehmann +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +entity config_tb is +end config_tb; + + +library PoC; +use PoC.config.all; +use PoC.utils.all; +use PoC.simulation.all; + + +architecture tb of config_tb is + signal SimQuiet : BOOLEAN := true; +begin + process + begin + if (SimQuiet = FALSE) then + report "is simulation?: " & boolean'image(SIMULATION) severity note; + report "Vendor: " & vendor_t'image(VENDOR) severity note; + report "Device: " & device_t'image(DEVICE) severity note; + report "Device Number: " & integer'image(DEVICE_NUMBER) severity note; + report "Device Subtype: " & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) severity note; + report "Device Series: " & integer'image(DEVICE_SERIES) severity note; + report "--------------------------------------------------" severity note; + report "LUT fan-in: " & integer'image(LUT_FANIN) severity note; + report "Transceiver: " & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) severity note; + end if; + + tbAssert((SIMULATION = TRUE), "SIMULATION=" & BOOLEAN'image(SIMULATION) & " Expected=TRUE"); + tbAssert((VENDOR = VENDOR_XILINX), "VENDOR= " & VENDOR_T'image(VENDOR) & " Expected=VENDOR_XILINX"); + tbAssert((DEVICE = DEVICE_KINTEX7), "DEVICE=" & DEVICE_T'image(DEVICE) & " Expected=DEVICE_KINTEX7"); + tbAssert((DEVICE_FAMILY = DEVICE_FAMILY_KINTEX), "DEVICE_FAMILY=" & T_DEVICE_FAMILY'image(DEVICE_FAMILY) & " Expected=DEVICE_FAMILY_KINTEX"); + tbAssert((DEVICE_NUMBER = 325), "DEVICE_NUMBER=" & INTEGER'image(DEVICE_NUMBER) & " Expected=325"); + tbAssert((DEVICE_SUBTYPE = DEVICE_SUBTYPE_T), "DEVICE_SUBTYPE=" & T_DEVICE_SUBTYPE'image(DEVICE_SUBTYPE) & " Expected=DEVICE_SUBTYPE_T"); + tbAssert((DEVICE_SERIES = 7), "DEVICE_SERIES=" & INTEGER'image(DEVICE_SERIES) & " Expected=7"); + tbAssert((LUT_FANIN = 6), "LUT_FANIN=" & INTEGER'image(LUT_FANIN) & " Expected=6"); + tbAssert((TRANSCEIVER_TYPE = TRANSCEIVER_GTXE2), "TRANSCEIVER_TYPE=" & T_TRANSCEIVER'image(TRANSCEIVER_TYPE) & " Expected=TRANSCEIVER_GTXE2"); + + -- simulation completed + + -- Report overall simulation result + tbPrintResult; + wait; + end process; +end; diff --git a/testsuite/gna/bug019/PoC/tb/common/my_config_ML505.vhdl b/testsuite/gna/bug019/PoC/tb/common/my_config_ML505.vhdl new file mode 100644 index 0000000..dd4634b --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/my_config_ML505.vhdl @@ -0,0 +1,48 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl. +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library PoC; + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "ML505"; -- ML505 - Xilinx Virtex 5 reference design board: XC5VLX50T + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + + -- For internal use only + constant MY_VERBOSE : boolean := FALSE; +end package; + +package body my_config is +end package body; diff --git a/testsuite/gna/bug019/PoC/tb/common/my_config_ML605.vhdl b/testsuite/gna/bug019/PoC/tb/common/my_config_ML605.vhdl new file mode 100644 index 0000000..90bb0ac --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/my_config_ML605.vhdl @@ -0,0 +1,50 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Thomas B. Preusser +-- Martin Zabel +-- Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl. +-- +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library PoC; + + +package my_config is + -- Change these lines to setup configuration. + constant MY_BOARD : string := "ML605"; -- ML605 - Xilinx Virtex 6 reference design board: XC6VLX240T + constant MY_DEVICE : string := "None"; -- infer from MY_BOARD + + -- For internal use only + constant MY_VERBOSE : boolean := FALSE; +end package; + + +package body my_config is + +end package body; diff --git a/testsuite/gna/bug019/PoC/tb/common/my_project.vhdl b/testsuite/gna/bug019/PoC/tb/common/my_project.vhdl new file mode 100644 index 0000000..84d03a8 --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/my_project.vhdl @@ -0,0 +1,52 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Patrick Lehmann +-- +-- Package: Project specific configuration. +-- +-- Description: +-- ------------------------------------ +-- This is a template file. +-- +-- TODO +-- +-- USAGE: +-- 1) Copy this file into your project's source directory and rename it to +-- "my_project.vhdl". +-- 2) Add file to library "poc" in your synthesis tool. +-- 3) Change setup appropriately. +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany, +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library PoC; + + +package my_project is + -- Change these lines to setup configuration. + constant MY_PROJECT_DIR : string := "."; + constant MY_OPERATING_SYSTEM : string := "LINUX"; -- e.g. "WINDOWS", "LINUX" +end package; + + +package body my_project is + +end package body; diff --git a/testsuite/gna/bug019/PoC/tb/common/simulation.v08.vhdl b/testsuite/gna/bug019/PoC/tb/common/simulation.v08.vhdl new file mode 100644 index 0000000..227158a --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/simulation.v08.vhdl @@ -0,0 +1,363 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Authors: Patrick Lehmann +-- Thomas B. Preusser +-- +-- Package: Simulation constants, functions and utilities. +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library PoC; +use PoC.vectors.all; +use PoC.strings.all; +use PoC.physical.all; + + +package simulation is + -- predefined constants to ease testvector concatenation + constant U8 : T_SLV_8 := (others => 'U'); + constant U16 : T_SLV_16 := (others => 'U'); + constant U24 : T_SLV_24 := (others => 'U'); + constant U32 : T_SLV_32 := (others => 'U'); + + constant D8 : T_SLV_8 := (others => '-'); + constant D16 : T_SLV_16 := (others => '-'); + constant D24 : T_SLV_24 := (others => '-'); + constant D32 : T_SLV_32 := (others => '-'); + + -- Testbench Status Management + -- =========================================================================== + + -- VHDL'08: Provide a protected tSimStatus type that may be used for + -- other purposes as well. For compatibility with the VHDL'93 + -- implementation, the plain procedure implementation is also + -- provided on top of a package private instance of this type. + + type T_TB_STATUS is protected + -- The status is changed to failed. If a message is provided, it is + -- reported as an error. + procedure simFail(msg : in string := ""); + + -- If the passed condition has evaluated false, the status is marked + -- as failed. In this case, the optional message will be reported as + -- an error if provided. + procedure simAssert(cond : in boolean; msg : in string := ""); + + -- Prints the final status. Unless simFail() or simAssert() with a + -- false condition have been called before, a successful completion + -- will be indicated, a failure otherwise. + procedure simReport; + end protected; + + type T_SIM_STATUS is protected + procedure stop; + impure function isStopped return BOOLEAN; + end protected; + + -- The testbench is marked as failed. If a message is provided, it is + -- reported as an error. + procedure tbFail(msg : in string := ""); + + -- If the passed condition has evaluated false, the testbench is marked + -- as failed. In this case, the optional message will be reported as an + -- error if one was provided. + procedure tbAssert(cond : in boolean; msg : in string := ""); + + -- Prints out the overall testbench result as defined by the automated + -- testbench process. Unless tbFail() or tbAssert() with a false condition + -- have been called before, a successful completion will be reported, a + -- failure otherwise. + procedure tbPrintResult; + + -- clock generation + -- =========================================================================== + subtype T_DutyCycle is REAL range 0.0 to 1.0; + + procedure simStop; + impure function simIsStopped return BOOLEAN; + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5); + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5); + + -- waveform generation + -- =========================================================================== + type T_SIM_WAVEFORM_TUPLE_SL is record + Delay : TIME; + Value : STD_LOGIC; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_8 is record + Delay : TIME; + Value : T_SLV_8; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_16 is record + Delay : TIME; + Value : T_SLV_16; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_24 is record + Delay : TIME; + Value : T_SLV_24; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_32 is record + Delay : TIME; + Value : T_SLV_32; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_48 is record + Delay : TIME; + Value : T_SLV_48; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_64 is record + Delay : TIME; + Value : T_SLV_64; + end record; + + type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL; + type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8; + type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16; + type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24; + type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32; + type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48; + type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64; + + procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN); + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0'); + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0'); + procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8); + procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16); + procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24); + procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32); + procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48); + procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64); + + function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC; + +end; + + +use std.TextIO.all; + +package body simulation is + -- Testbench Status Management + -- =========================================================================== + type T_TB_STATUS is protected body + -- Internal state variable to log a failure condition for final reporting. + -- Once de-asserted, this variable will never return to a value of true. + variable pass : boolean := true; + + procedure simFail(msg : in string := "") is + begin + if msg'length > 0 then + report msg severity error; + end if; + pass := false; + end; + + procedure simAssert(cond : in boolean; msg : in string := "") is + begin + if not cond then + simFail(msg); + end if; + end; + + procedure simReport is + variable l : line; + begin + write(l, string'("SIMULATION RESULT = ")); + if pass then + write(l, string'("PASSED")); + else + write(l, string'("FAILED")); + end if; + writeline(output, l); + end; + end protected body; + + type T_SIM_STATUS is protected body + variable stopped : BOOLEAN := FALSE; + + procedure stop is + begin + stopped := TRUE; + end procedure; + + impure function isStopped return BOOLEAN is + begin + return stopped; + end function; + end protected body; + + -- The default global tSimStatus object. + shared variable tbStatus : T_TB_STATUS; + shared variable simStatus : T_SIM_STATUS; + + -- legacy procedures + -- =========================================================================== + procedure tbFail(msg : in string := "") is + begin + tbStatus.simFail(msg); + end; + + procedure tbAssert(cond : in boolean; msg : in string := "") is + begin + tbStatus.simAssert(cond, msg); + end; + + procedure tbPrintResult is + begin + tbStatus.simReport; + end procedure; + + -- clock generation + -- =========================================================================== + procedure simStop is + begin + simStatus.stop; + end procedure; + + impure function simIsStopped return BOOLEAN is + begin + return simStatus.isStopped; + end function; + + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is + constant Period : TIME := to_time(Frequency); + begin + simGenerateClock(Clock, Period, DutyCycle); + end procedure; + + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is + constant TIME_HIGH : TIME := Period * DutyCycle; + constant TIME_LOW : TIME := Period - TIME_HIGH; + begin + Clock <= '0'; + + while (not simStatus.isStopped) loop + wait for TIME_LOW; + Clock <= '1'; + wait for TIME_HIGH; + Clock <= '0'; + end loop; + end procedure; + + -- waveform generation + -- =========================================================================== + procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is + variable State : BOOLEAN := InitialValue; + begin + Wave <= State; + for i in Waveform'range loop + wait for Waveform(i); + State := not State; + Wave <= State; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is + variable State : STD_LOGIC := InitialValue; + begin + Wave <= State; + for i in Waveform'range loop + wait for Waveform(i); + State := not State; + Wave <= State; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is + begin + return (0 => Pause, 1 => ResetPulse); + end function; +end package body; diff --git a/testsuite/gna/bug019/PoC/tb/common/simulation.v93.vhdl b/testsuite/gna/bug019/PoC/tb/common/simulation.v93.vhdl new file mode 100644 index 0000000..22e6009 --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/simulation.v93.vhdl @@ -0,0 +1,308 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Testbench: Simulation constants, functions and utilities. +-- +-- Authors: Patrick Lehmann +-- Thomas B. Preusser +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2014 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +library IEEE; +use IEEE.STD_LOGIC_1164.all; + +library PoC; +use PoC.vectors.all; +use PoC.strings.all; +use PoC.physical.all; + + +package simulation is + -- predefined constants to ease testvector concatenation + constant U8 : T_SLV_8 := (others => 'U'); + constant U16 : T_SLV_16 := (others => 'U'); + constant U24 : T_SLV_24 := (others => 'U'); + constant U32 : T_SLV_32 := (others => 'U'); + + constant D8 : T_SLV_8 := (others => '-'); + constant D16 : T_SLV_16 := (others => '-'); + constant D24 : T_SLV_24 := (others => '-'); + constant D32 : T_SLV_32 := (others => '-'); + + -- Testbench Status Management + -- =========================================================================== + -- The testbench is marked as failed. If a message is provided, it is + -- reported as an error. + procedure tbFail(msg : in string := ""); + + -- If the passed condition has evaluated false, the testbench is marked + -- as failed. In this case, the optional message will be reported as an + -- error if one was provided. + procedure tbAssert(cond : in boolean; msg : in string := ""); + + -- Prints out the overall testbench result as defined by the automated + -- testbench process. Unless tbFail() or tbAssert() with a false condition + -- have been called before, a successful completion will be reported, a + -- failure otherwise. + procedure tbPrintResult; + + -- clock generation + -- =========================================================================== + subtype T_DutyCycle is REAL range 0.0 to 1.0; + + procedure simStop; + impure function simIsStopped return BOOLEAN; + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5); + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5); + + -- waveform generation + -- =========================================================================== + type T_SIM_WAVEFORM_TUPLE_SL is record + Delay : TIME; + Value : STD_LOGIC; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_8 is record + Delay : TIME; + Value : T_SLV_8; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_16 is record + Delay : TIME; + Value : T_SLV_16; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_24 is record + Delay : TIME; + Value : T_SLV_24; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_32 is record + Delay : TIME; + Value : T_SLV_32; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_48 is record + Delay : TIME; + Value : T_SLV_48; + end record; + + type T_SIM_WAVEFORM_TUPLE_SLV_64 is record + Delay : TIME; + Value : T_SLV_64; + end record; + + type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL; + type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8; + type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16; + type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24; + type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32; + type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48; + type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64; + + procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform: T_TIMEVEC; InitialValue : BOOLEAN); + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0'); + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0'); + procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8); + procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16); + procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24); + procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32); + procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48); + procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64); + + function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC; + + -- TODO: integrate VCD simulation functions and procedures from sim_value_change_dump.vhdl here + + -- checksum functions + -- =========================================================================== + -- TODO: move checksum functions here +end; + + +use std.TextIO.all; + +package body simulation is + + -- Testbench Status Management + -- =========================================================================== + -- Internal state variable to log a failure condition for final reporting. + -- Once de-asserted, this variable will never return to a value of true. + shared variable pass : boolean := true; + shared variable simStopped : BOOLEAN := FALSE; + + procedure tbFail(msg : in string := "") is + begin + if (str_length(msg) > 0) then + report str_trim(msg) severity error; + end if; + pass := false; + end; + + procedure tbAssert(cond : in boolean; msg : in string := "") is + begin + if not cond then + tbFail(msg); + end if; + end; + + procedure tbPrintResult is + variable l : line; + begin + write(l, string'("SIMULATION RESULT = ")); + if pass then + write(l, string'("PASSED")); + else + write(l, string'("FAILED")); + end if; + writeline(output, l); + end procedure; + + -- clock generation + procedure simStop is + begin + simStopped := TRUE; + end procedure; + + impure function simIsStopped return BOOLEAN is + begin + return simStopped; + end function; + + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Frequency : in FREQ; constant DutyCycle : T_DutyCycle := 0.5) is + constant Period : TIME := to_time(Frequency); + begin + simGenerateClock(Clock, Period, DutyCycle); + end procedure; + + procedure simGenerateClock(signal Clock : out STD_LOGIC; constant Period : in TIME; constant DutyCycle : T_DutyCycle := 0.5) is + constant TIME_HIGH : TIME := Period * DutyCycle; + constant TIME_LOW : TIME := Period - TIME_HIGH; + begin + Clock <= '0'; + + while (not simStopped) loop + wait for TIME_LOW; + Clock <= '1'; + wait for TIME_HIGH; + Clock <= '0'; + end loop; + end procedure; + + -- waveform generation + procedure simGenerateWaveform(signal Wave : out BOOLEAN; Waveform : T_TIMEVEC; InitialValue : BOOLEAN) is + variable State : BOOLEAN := InitialValue; + begin + Wave <= State; + for i in Waveform'range loop + wait for Waveform(i); + State := not State; + Wave <= State; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_TIMEVEC; InitialValue : STD_LOGIC := '0') is + variable State : STD_LOGIC := InitialValue; + begin + Wave <= State; + for i in Waveform'range loop + wait for Waveform(i); + State := not State; + Wave <= State; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out STD_LOGIC; Waveform: T_SIM_WAVEFORM_SL; InitialValue : STD_LOGIC := '0') is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_8; Waveform: T_SIM_WAVEFORM_SLV_8; InitialValue : T_SLV_8) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_16; Waveform: T_SIM_WAVEFORM_SLV_16; InitialValue : T_SLV_16) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_24; Waveform: T_SIM_WAVEFORM_SLV_24; InitialValue : T_SLV_24) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_32; Waveform: T_SIM_WAVEFORM_SLV_32; InitialValue : T_SLV_32) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_48; Waveform: T_SIM_WAVEFORM_SLV_48; InitialValue : T_SLV_48) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + procedure simGenerateWaveform(signal Wave : out T_SLV_64; Waveform: T_SIM_WAVEFORM_SLV_64; InitialValue : T_SLV_64) is + begin + Wave <= InitialValue; + for i in Waveform'range loop + wait for Waveform(i).Delay; + Wave <= Waveform(i).Value; + end loop; + end procedure; + + function simGenerateWaveform_Reset(constant Pause : TIME := 0 ns; ResetPulse : TIME := 10 ns) return T_TIMEVEC is + begin + return (0 => Pause, 1 => ResetPulse); + end function; + + -- checksum functions + -- =========================================================================== + -- TODO: move checksum functions here +end package body; diff --git a/testsuite/gna/bug019/PoC/tb/common/strings_tb.vhdl b/testsuite/gna/bug019/PoC/tb/common/strings_tb.vhdl new file mode 100644 index 0000000..30e3b5c --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/common/strings_tb.vhdl @@ -0,0 +1,123 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================= +-- Testbench: Tests global constants, functions and settings +-- +-- Authors: Patrick Lehmann +-- +-- Description: +-- ------------------------------------ +-- TODO +-- +-- License: +-- ============================================================================= +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================= + +entity strings_tb is +end strings_tb; + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.config.all; +use PoC.utils.all; +use PoC.strings.all; +use PoC.simulation.all; + + +architecture tb of strings_tb is + constant raw_format_slv_dec_result0 : STRING := raw_format_slv_dec(STD_LOGIC_VECTOR'(x"12")); + constant raw_format_slv_dec_result1 : STRING := raw_format_slv_dec(x"3456"); + constant raw_format_slv_dec_result2 : STRING := raw_format_slv_dec(x"12345678"); + constant raw_format_slv_dec_result3 : STRING := raw_format_slv_dec(x"A1B2C3D4E5F607A8"); + + constant str_length_result0 : INTEGER := str_length(""); + constant str_length_result1 : INTEGER := str_length((1 to 3 => C_POC_NUL)); + constant str_length_result2 : INTEGER := str_length("Hello"); + constant str_length_result3 : INTEGER := str_length("Hello" & (1 to 3 => C_POC_NUL)); + + constant str_match_result0 : BOOLEAN := str_match("", ""); + constant str_match_result1 : BOOLEAN := str_match("", (1 to 3 => C_POC_NUL)); + constant str_match_result2 : BOOLEAN := str_match("Hello", "hello"); + constant str_match_result3 : BOOLEAN := str_match("Hello", "Hello"); + constant str_match_result4 : BOOLEAN := str_match("Hello World", "Hello"); + constant str_match_result5 : BOOLEAN := str_match("Hello", "Hello World"); + constant str_match_result6 : BOOLEAN := str_match("Hello", "Hello" & (1 to 3 => C_POC_NUL)); + + constant str_imatch_result0 : BOOLEAN := str_imatch("", ""); + constant str_imatch_result1 : BOOLEAN := str_imatch("", (1 to 3 => C_POC_NUL)); + constant str_imatch_result2 : BOOLEAN := str_imatch("Hello", "hello"); + constant str_imatch_result3 : BOOLEAN := str_imatch("Hello", "Hello"); + constant str_imatch_result4 : BOOLEAN := str_imatch("Hello World", "Hello"); + constant str_imatch_result5 : BOOLEAN := str_imatch("Hello", "Hello World"); + constant str_imatch_result6 : BOOLEAN := str_imatch("Hello", "Hello" & (1 to 3 => C_POC_NUL)); +begin + process + begin + -- raw_format_slv_dec tests + tbAssert((raw_format_slv_dec_result0 = "18"), "raw_format_slv_dec(0x12)=" & raw_format_slv_dec_result0 & " Expected='18'"); + tbAssert((raw_format_slv_dec_result1 = "13398"), "raw_format_slv_dec(0x3456)=" & raw_format_slv_dec_result1 & " Expected='13398'"); + tbAssert((raw_format_slv_dec_result2 = "305419896"), "raw_format_slv_dec(0x12345678)=" & raw_format_slv_dec_result2 & " Expected='305419896'"); + tbAssert((raw_format_slv_dec_result3 = "11651590505119483816"), "raw_format_slv_dec(0xA1b2c3d4e5f607a8)=" & raw_format_slv_dec_result3 & " Expected='11651590505119483816'"); + + -- str_length tests + tbAssert((str_length_result0 = 0), "str_length('')=" & INTEGER'image(str_length_result0) & " Expected=0"); + tbAssert((str_length_result1 = 0), "str_length('\0\0\0')=" & INTEGER'image(str_length_result1) & " Expected=0"); + tbAssert((str_length_result2 = 5), "str_length('Hello')=" & INTEGER'image(str_length_result2) & " Expected=5"); + tbAssert((str_length_result3 = 5), "str_length('Hello\0\0\0')=" & INTEGER'image(str_length_result3) & " Expected=5"); + + -- str_match tests + tbAssert((str_match_result0 = TRUE), "str_match('', '')=" & BOOLEAN'image(str_match_result0) & " Expected=TRUE"); + tbAssert((str_match_result1 = TRUE), "str_match('', '\0\0\0')=" & BOOLEAN'image(str_match_result1) & " Expected=TRUE"); + tbAssert((str_match_result2 = FALSE), "str_match('Hello', 'hello')=" & BOOLEAN'image(str_match_result2) & " Expected=FALSE"); + tbAssert((str_match_result3 = TRUE), "str_match('Hello', 'Hello')=" & BOOLEAN'image(str_match_result3) & " Expected=TRUE"); + tbAssert((str_match_result4 = FALSE), "str_match('Hello World', 'Hello')=" & BOOLEAN'image(str_match_result4) & " Expected=FALSE"); + tbAssert((str_match_result5 = FALSE), "str_match('Hello', 'Hello World')=" & BOOLEAN'image(str_match_result5) & " Expected=FALSE"); + tbAssert((str_match_result6 = TRUE), "str_match('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_match_result6) & " Expected=TRUE"); + + -- str_imatch tests + tbAssert((str_imatch_result0 = TRUE), "str_imatch('', '')=" & BOOLEAN'image(str_imatch_result0) & " Expected=TRUE"); + tbAssert((str_imatch_result1 = TRUE), "str_imatch('', '\0\0\0')=" & BOOLEAN'image(str_imatch_result1) & " Expected=TRUE"); + tbAssert((str_imatch_result2 = TRUE), "str_imatch('Hello', 'hello')=" & BOOLEAN'image(str_imatch_result2) & " Expected=TRUE"); + tbAssert((str_imatch_result3 = TRUE), "str_imatch('Hello', 'Hello')=" & BOOLEAN'image(str_imatch_result3) & " Expected=TRUE"); + tbAssert((str_imatch_result4 = FALSE), "str_imatch('Hello World', 'Hello')=" & BOOLEAN'image(str_imatch_result4) & " Expected=FALSE"); + tbAssert((str_imatch_result5 = FALSE), "str_imatch('Hello', 'Hello World')=" & BOOLEAN'image(str_imatch_result5) & " Expected=FALSE"); + tbAssert((str_imatch_result6 = TRUE), "str_imatch('Hello', 'Hello\0\0\0')=" & BOOLEAN'image(str_imatch_result6) & " Expected=TRUE"); + + -- str_pos tests + -- str_ipos tests + -- str_find tests + -- str_ifind tests + -- str_replace tests + -- str_substr tests + -- str_ltrim tests + -- str_rtrim tests + -- str_trim tests + -- str_toLower tests + -- str_toUpper tests + + -- simulation completed + + -- Report overall simulation result + tbPrintResult; + wait; + end process; +end; diff --git a/testsuite/gna/bug019/PoC/tb/io/uart/uart_rx_tb.vhdl b/testsuite/gna/bug019/PoC/tb/io/uart/uart_rx_tb.vhdl new file mode 100644 index 0000000..166f74e --- /dev/null +++ b/testsuite/gna/bug019/PoC/tb/io/uart/uart_rx_tb.vhdl @@ -0,0 +1,141 @@ +-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- +-- vim: tabstop=2:shiftwidth=2:noexpandtab +-- kate: tab-width 2; replace-tabs off; indent-width 2; +-- +-- ============================================================================ +-- Module: uart_rx_tb +-- +-- Authors: Patrick Lehmann +-- +-- Description: +-- ------------------------------------ +-- Testbench for arith_counter_bcd +-- +-- License: +-- ============================================================================ +-- Copyright 2007-2015 Technische Universitaet Dresden - Germany +-- Chair for VLSI-Design, Diagnostics and Architecture +-- +-- Licensed under the Apache License, Version 2.0 (the "License"); +-- you may not use this file except in compliance with the License. +-- You may obtain a copy of the License at +-- +-- http://www.apache.org/licenses/LICENSE-2.0 +-- +-- Unless required by applicable law or agreed to in writing, software +-- distributed under the License is distributed on an "AS IS" BASIS, +-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +-- See the License for the specific language governing permissions and +-- limitations under the License. +-- ============================================================================ + +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +library PoC; +use PoC.utils.all; +use PoC.vectors.all; +use PoC.strings.all; +use PoC.physical.all; +use PoC.simulation.all; +use PoC.uart.all; + + +entity uart_rx_tb is +end entity; + + +architecture tb of uart_rx_tb is + constant CLOCK_FREQ : FREQ := 100 MHz; + constant BAUDRATE : BAUD := 4.2 MBd; + + signal Clock : STD_LOGIC; + signal Reset : STD_LOGIC; + + signal BitClock : STD_LOGIC; + signal BitClock_x8 : STD_LOGIC; + + signal UART_RX : STD_LOGIC; + + signal RX_Strobe : STD_LOGIC; + signal RX_Data : T_SLV_8; + + function simGenerateWaveform_UART_Word(Data : T_SLV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is + constant BIT_TIME : TIME := to_time(to_freq(Baudrate)); + variable Result : T_SIM_WAVEFORM_SL(0 to 9) := (others => (Delay => BIT_TIME, Value => '-')); + begin + Result(0).Value := '0'; + for i in Data'range loop + Result(i + 1).Value := Data(i); + end loop; + Result(9).Value := '1'; + return Result; + end function; + + function simGenerateWaveform_UART_Stream(Data : T_SLVV_8; Baudrate : BAUD := 115.200 kBd) return T_SIM_WAVEFORM_SL is + variable Result : T_SIM_WAVEFORM_SL(0 to (Data'length * 10) - 1); + begin + for i in Data'range loop + Result(i * 10 to ((i + 1) * 10) - 1) := simGenerateWaveform_UART_Word(Data(i), BAUDRATE); + end loop; + return Result; + end function; + + constant DATA_STREAM : T_SLVV_8 := (x"12", x"45", x"FE", x"C4", x"02"); + +begin + simGenerateClock(Clock, CLOCK_FREQ); + simGenerateWaveform(Reset, simGenerateWaveform_Reset(Pause => 50 ns)); + p1f: if true generate + simGenerateWaveform(UART_RX, simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE), '1'); + end generate; + p1t: if false generate + process + constant wf : T_SIM_WAVEFORM_SL := simGenerateWaveform_UART_Stream(DATA_STREAM, BAUDRATE); + begin + simGenerateWaveform(UART_RX, wf, '1'); + end process; + end generate; + + bclk : entity PoC.uart_bclk + generic map ( + CLOCK_FREQ => CLOCK_FREQ, + BAUDRATE => BAUDRATE + ) + port map ( + clk => Clock, + rst => Reset, + bclk => BitClock, + bclk_x8 => BitClock_x8 + ); + + RX : entity PoC.uart_rx + generic map ( + OUT_REGS => FALSE + ) + port map ( + clk => Clock, + rst => Reset, + bclk_x8 => BitClock_x8, + dos => RX_Strobe, + dout => RX_Data, + rxd => UART_RX + ); + + process + begin + for i in DATA_STREAM'range loop + wait until rising_edge(Clock) and (RX_Strobe = '1'); + report TIME'image(NOW) severity NOTE; + tbAssert((RX_Data = DATA_STREAM(i)), "Data Byte " & INTEGER'image(i) & " received: " & to_string(RX_Data, 'h') & " expected: " & to_string(DATA_STREAM(i), 'h')); + end loop; + + wait for 1 us; + simStop; + + tbPrintResult; + wait; + end process; + +end architecture; |