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-rw-r--r--src/vhdl/translate/translation.adb5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/vhdl/translate/translation.adb b/src/vhdl/translate/translation.adb
index 2d89a62..b20f622 100644
--- a/src/vhdl/translate/translation.adb
+++ b/src/vhdl/translate/translation.adb
@@ -199,9 +199,8 @@ package body Translation is
is
Info : Design_File_Info_Acc;
begin
- if Current_Filename_Node /= O_Dnode_Null then
- raise Internal_Error;
- end if;
+ pragma Assert (Current_Filename_Node = O_Dnode_Null);
+
Info := Get_Info (Design_File);
if Info = null then
Info := Add_Info (Design_File, Kind_Design_File);