6 files changed, 169 insertions, 0 deletions
diff --git a/testsuite/gna/ticket14/repro.vhdl b/testsuite/gna/ticket14/repro.vhdl
new file mode 100644
index 0000000..6d89fbc
--- /dev/null
+++ b/testsuite/gna/ticket14/repro.vhdl
@@ -0,0 +1,22 @@
+entity repro is
+    generic (
+	BUS_WIDTH : integer := 8;
+	ARRAY_WIDTH : integer := 2);
+end entity repro;
+
+architecture behavioural of repro is
+
+    type test_array_type is array (ARRAY_WIDTH-1 downto 0) of
+      bit_vector (BUS_WIDTH-1 downto 0);
+    signal s : test_array_type := (others => (others => '0'));
+
+begin
+
+    failing_process : process
+    begin
+      assert s'left = 1;
+      assert s'right = 0;
+      wait;
+    end process failing_process;
+    
+end architecture behavioural;
diff --git a/testsuite/gna/ticket14/reprook.vhdl b/testsuite/gna/ticket14/reprook.vhdl
new file mode 100644
index 0000000..0d026a7
--- /dev/null
+++ b/testsuite/gna/ticket14/reprook.vhdl
@@ -0,0 +1,23 @@
+entity reprook is
+    generic (
+	BUS_WIDTH : integer := 8;
+	ARRAY_WIDTH : integer := 2);
+end entity reprook;
+
+architecture behavioural of reprook is
+
+    type test_array_btype is array (integer range <>) of
+      bit_vector (BUS_WIDTH-1 downto 0);
+    subtype test_array_type is test_array_btype (ARRAY_WIDTH-1 downto 0);
+    signal s : test_array_type := (others => (others => '0'));
+
+begin
+
+    failing_process : process
+    begin
+      assert s'left = 1;
+      assert s'right = 0;
+      wait;
+    end process failing_process;
+    
+end architecture behavioural;
diff --git a/testsuite/gna/ticket14/scrambler_tb.vhd b/testsuite/gna/ticket14/scrambler_tb.vhd
new file mode 100644
index 0000000..97b7ef3
--- /dev/null
+++ b/testsuite/gna/ticket14/scrambler_tb.vhd
@@ -0,0 +1,50 @@
+library ieee;
+use ieee.std_logic_1164.all;
+ 
+entity scrambler_tb is
+end entity scrambler_tb;
+ 
+architecture behaviour of scrambler_tb is
+
+    constant clk_period : time := 10 ns;
+    
+    signal clk, reset : std_logic;
+    signal en, seed : std_logic;
+    signal d_in, d_out : std_logic;
+
+begin 
+
+    uut: entity work.scrambler
+	port map (
+	    clk => clk,
+	    reset => reset,
+	    en => en,
+	    seed => seed,
+	    d_in => d_out,
+	    d_out => d_out);
+		  
+   -- Clock process definitions
+    clk_process: process
+    begin
+      for i in 1 to 10 loop
+	clk <= '0';
+	wait for clk_period/2;
+	clk <= '1';
+	wait for clk_period/2;
+      end loop;
+      wait;
+    end process;
+
+    -- Stimulus process
+    stim_proc: process begin		
+
+	-- Reset period
+	reset <= '1';
+	wait for clk_period * 2;	
+	reset <= '0';
+	wait for clk_period * 3.5;
+
+	wait;
+   end process;
+
+end architecture behaviour;
diff --git a/testsuite/gna/ticket14/tb.vhd b/testsuite/gna/ticket14/tb.vhd
new file mode 100644
index 0000000..3b6c50e
--- /dev/null
+++ b/testsuite/gna/ticket14/tb.vhd
@@ -0,0 +1,32 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb is
+
+end tb;
+
+architecture behav of tb is
+  signal clk : std_logic;
+begin  -- behav
+
+  process
+  begin
+    for i in 1 to 5 loop
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end loop;  -- i
+  end process;
+
+  inst : entity work.scrambler port map (
+    clk   => clk,
+    en    => '0',
+    reset => '0',
+    seed  => '0',
+    d_in  => '0',
+    d_out => open);
+
+end behav;
diff --git a/testsuite/gna/ticket14/test_case.vhd b/testsuite/gna/ticket14/test_case.vhd
new file mode 100644
index 0000000..e8c8ec9
--- /dev/null
+++ b/testsuite/gna/ticket14/test_case.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+-- use ieee.numeric_std.all;
+
+entity scrambler is
+    generic (
+	BUS_WIDTH : integer := 8;
+	ARRAY_WIDTH : integer := 2);
+    port (
+	clk, en, reset, seed : in std_logic;
+	d_in : in std_logic;
+	d_out : out std_logic);
+end entity scrambler;
+
+architecture behavioural of scrambler is
+
+    type test_array_type is array (ARRAY_WIDTH-1 downto 0) of
+      std_logic_vector (BUS_WIDTH-1 downto 0);
+    signal test_array : test_array_type := (others => (others => '0'));
+    signal test_vec : std_logic_vector (BUS_WIDTH-1 downto 0) 
+					:= (others => '0');
+
+begin
+
+    failing_process : process (clk) begin
+	if clk'event and clk = '1' then
+	    test_array <= test_array (ARRAY_WIDTH-2 downto 0) & test_vec;
+	end if;
+    end process failing_process;
+    
+end architecture behavioural;
diff --git a/testsuite/gna/ticket14/testsuite.sh b/testsuite/gna/ticket14/testsuite.sh
new file mode 100755
index 0000000..9f9d350
--- /dev/null
+++ b/testsuite/gna/ticket14/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze test_case.vhd
+analyze scrambler_tb.vhd
+elab_simulate scrambler_tb
+
+clean
+
+echo "Test successful"