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-rw-r--r--testsuite/gna/bug06/repro.vhdl29
-rwxr-xr-xtestsuite/gna/bug06/testsuite.sh10
2 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/gna/bug06/repro.vhdl b/testsuite/gna/bug06/repro.vhdl
new file mode 100644
index 0000000..02b275d
--- /dev/null
+++ b/testsuite/gna/bug06/repro.vhdl
@@ -0,0 +1,29 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity foo is
+end entity;
+architecture fum of foo is
+ constant A: std_logic_vector (7 downto 0) := X"04";
+
+ function slv_image(inp: std_logic_vector) return string is
+ variable image_str: string (1 to inp'length);
+ alias input_str: std_logic_vector (1 to inp'length) is inp;
+ begin
+ for i in input_str'range loop
+ image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
+ end loop;
+ return image_str;
+ end;
+
+begin
+SOME_LABEL:
+ process
+ begin
+ wait for 1 ns;
+ if A <= "00001011" then -- if A <= std_logic_vector'("00001011") then
+ report "A = " & slv_image(A) ;
+ end if;
+ wait;
+ end process;
+end architecture;
diff --git a/testsuite/gna/bug06/testsuite.sh b/testsuite/gna/bug06/testsuite.sh
new file mode 100755
index 0000000..f98b814
--- /dev/null
+++ b/testsuite/gna/bug06/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze repro.vhdl
+elab_simulate foo
+
+clean
+
+echo "Test successful"