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authorTristan Gingold2015-01-10 08:16:19 +0100
committerTristan Gingold2015-01-10 08:16:19 +0100
commitfafa25a6c0a1365bed4990e26d151e8140797730 (patch)
tree4610116cc944a35133e131508182eddfee043b51 /testsuite
parentb467c5bb8e0c5e56eb756bf40a9dd548ef4c0633 (diff)
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Add testcase from ticket31.
Diffstat (limited to 'testsuite')
-rw-r--r--testsuite/gna/ticket31/tb2.vhdl12
-rwxr-xr-xtestsuite/gna/ticket31/testsuite.sh13
-rw-r--r--testsuite/gna/ticket31/top_phystest_simple.vhdl22
3 files changed, 47 insertions, 0 deletions
diff --git a/testsuite/gna/ticket31/tb2.vhdl b/testsuite/gna/ticket31/tb2.vhdl
new file mode 100644
index 0000000..4b19220
--- /dev/null
+++ b/testsuite/gna/ticket31/tb2.vhdl
@@ -0,0 +1,12 @@
+entity Tb2 is
+end;
+
+architecture top of Tb2 is
+ function get_m15 return real is
+ begin
+ return -1.5;
+ end get_m15;
+ constant int_2 : INTEGER := natural(get_m15);
+begin
+ assert FALSE report "17 - int_2 (natural(-1.5)): " & INTEGER'image(int_2) severity note;
+end;
diff --git a/testsuite/gna/ticket31/testsuite.sh b/testsuite/gna/ticket31/testsuite.sh
new file mode 100755
index 0000000..d71d3ef
--- /dev/null
+++ b/testsuite/gna/ticket31/testsuite.sh
@@ -0,0 +1,13 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze top_phystest_simple.vhdl
+elab_simulate_failure top_physicaltest_simple
+
+analyze tb2.vhdl
+elab_simulate_failure tb2
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/ticket31/top_phystest_simple.vhdl b/testsuite/gna/ticket31/top_phystest_simple.vhdl
new file mode 100644
index 0000000..fd88e62
--- /dev/null
+++ b/testsuite/gna/ticket31/top_phystest_simple.vhdl
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.MATH_REAL.all;
+
+entity Top_PhysicalTest_Simple is
+ port (
+ Clock : in STD_LOGIC;
+ Input : in STD_LOGIC;
+ Output : out STD_LOGIC
+ );
+end;
+
+architecture top of Top_PhysicalTest_Simple is
+ constant int_1 : INTEGER := natural(1.5);
+ -- constant int_2 : INTEGER := integer(-1.5);
+ constant int_2 : INTEGER := natural(-1.5);
+begin
+ assert FALSE report "16 - int_1 (natural(1.5)): " & INTEGER'image(int_1) severity note;
+ assert FALSE report "17 - int_2 (natural(-1.5)): " & INTEGER'image(int_2) severity note;
+
+ Output <= Input when rising_edge(Clock);
+end;