Add sr2676 test.

6 files changed, 310 insertions, 0 deletions

diff --git a/testsuite/gna/sr2676/Makefile b/testsuite/gna/sr2676/Makefile
new file mode 100644
index 0000000..620744c
--- /dev/null
+++ b/testsuite/gna/sr2676/Makefile
@@ -0,0 +1,31 @@
+# project name
+PROJECT=reset
+# vhdl files
+FILES = reset.vhdl reset_types.vhdl reset-rtl.vhdl
+# testbench
+SIMTOP = reset_testbench
+SIMFILES = reset-test.vhdl
+# Simu break condition
+GHDL_SIM_OPT    = --assert-level=error --ieee-asserts=disable
+#GHDL_SIM_OPT    = --stop-time=1ms
+SIMDIR = sim
+
+GHDL_CMD        = ghdl
+GHDL_FLAGS      = --warn-no-vital-generic 
+VIEW_CMD        = /usr/bin/gtkwave
+
+ghdl-compile:
+	mkdir -p $(SIMDIR)
+	$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=$(SIMDIR) --work=work $(SIMFILES) $(FILES)
+	$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=$(SIMDIR) --work=work $(SIMTOP)
+	@mv $(SIMTOP) $(SIMDIR)/$(SIMTOP)
+
+ghdl-run: ghdl-compile
+	@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
+
+ghdl-view: 
+	gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd &
+
+ghdl-clean :
+
+
diff --git a/testsuite/gna/sr2676/reset-rtl.vhdl b/testsuite/gna/sr2676/reset-rtl.vhdl
new file mode 100644
index 0000000..722661f
--- /dev/null
+++ b/testsuite/gna/sr2676/reset-rtl.vhdl
@@ -0,0 +1,120 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.reset_types.all;
+
+architecture rtl of power_on_reset is
+	--signal current_state: reset_state;
+	signal current_state: reset_state;
+	signal next_state: reset_state;
+	signal por_counter: unsigned(31 downto 0);
+	signal saved_por_counter: unsigned(31 downto 0);
+
+	constant DELAY_POWER_STABLE_CLOCKS: unsigned := to_unsigned((10 * 1000), 32)/clk_period_ns;
+	constant DELAY_PM_READ_ID_CLOCKS: unsigned := 
+		DELAY_POWER_STABLE_CLOCKS + to_unsigned((10 * 1000), 32)/clk_period_ns;
+	constant DELAY_PM_READ_ID_DONE_CLOCKS: unsigned := 
+		DELAY_PM_READ_ID_CLOCKS + to_unsigned((10 * 1000), 32)/clk_period_ns;
+	
+
+begin
+
+-- advance the state variable and detect reset 
+advance_state: process(clk, reset)
+begin
+	if (reset = '1') then
+		current_state <= RST;
+	elsif rising_edge(clk) then
+		current_state <= next_state;
+	end if;
+end process advance_state;
+
+run_counter: process(clk, current_state)
+begin
+	if (current_state = RST) then
+		por_counter <= (others => '0');
+	elsif (current_State = MONITOR_RESET) then
+		por_counter <= por_counter;
+	else
+		por_counter <= por_counter + 1;
+	end if;
+end process run_counter;
+
+-- select the next state
+select_state: process(clk)
+begin
+	sys_clken <= '1';
+	core_en <= '1';
+	case current_state is
+		when RST =>
+			core_en <= '0';
+			sys_clken <= '0';
+			clk_33mhz_en <= '0';
+			cfg_drv <= '0';
+			rd_pmbrd_rev <= '0';
+			next_state <= ENABLE_CORE_POWER;
+	
+		when ENABLE_CORE_POWER =>
+			if (por_counter < DELAY_POWER_STABLE_CLOCKS) then
+				-- wait for core power to stabilize
+				next_state <= ENABLE_CORE_POWER;
+			else
+				next_state <= SELECT_PROCESSOR_POR_CONFIG;
+			end if;
+
+		when SELECT_PROCESSOR_POR_CONFIG =>
+			cfg_drv <= '1';
+			next_state <= SAMPLE_HW_CONFIG;
+
+		when SAMPLE_HW_CONFIG =>
+			if (por_counter < DELAY_PM_READ_ID_CLOCKS) then
+				-- delay until ready to read personality module ID
+				next_state <= SAMPLE_HW_CONFIG;
+			else
+				next_state <= SELECT_PERSONALITY_ID;
+			end if;
+
+		when SELECT_PERSONALITY_ID =>
+			rd_pmbrd_rev <= '1';
+			next_state <= SAMPLE_PERSONALITY_ID;
+
+		when SAMPLE_PERSONALITY_ID =>
+			if (por_counter < DELAY_PM_READ_ID_DONE_CLOCKS) then
+				next_state <= SAMPLE_PERSONALITY_ID;
+			else
+				next_state <= DESELECT_PERSONALITY_ID;
+			end if;
+
+		when DESELECT_PERSONALITY_ID =>
+			rd_pmbrd_rev <= '0';
+			next_state <= DEASSERT_HRESET;
+
+		when DEASSERT_HRESET =>
+			saved_por_counter <= por_counter;
+			if (por_counter < (saved_por_counter + 4)) then
+				next_state <= DEASSERT_HRESET;
+			else
+				next_state <= DESELECT_PROCESSOR_POR_CONFIG;
+			end if;
+
+		when DESELECT_PROCESSOR_POR_CONFIG =>
+			cfg_drv <= '0';
+			next_state <= WAIT_FOR_PROCESSOR;
+
+		when WAIT_FOR_PROCESSOR =>
+			next_state <= ENABLE_ALL_DEVICES;
+
+		when ENABLE_ALL_DEVICES =>
+			next_state <= MONITOR_RESET;
+
+		when MONITOR_RESET =>
+			next_state <= MONITOR_RESET;
+	end case;
+end process select_state;
+
+-- output state variable
+cur_state <= current_state;
+
+end rtl;
+
+
diff --git a/testsuite/gna/sr2676/reset-test.vhdl b/testsuite/gna/sr2676/reset-test.vhdl
new file mode 100644
index 0000000..3a9607e
--- /dev/null
+++ b/testsuite/gna/sr2676/reset-test.vhdl
@@ -0,0 +1,100 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use std.textio.all;
+use ieee.numeric_std.all;
+
+use work.reset_types.all;
+
+entity reset_testbench is
+end reset_testbench;
+
+architecture behavior of reset_testbench is
+
+component power_on_reset
+	port (
+		clk: in std_logic;
+		reset: in std_logic;
+
+		core_en: out std_logic;
+		sys_clken: out std_logic;
+		cfg_drv: out std_logic;
+		rd_pmbrd_rev : out std_logic;
+
+		clk_33mhz_en: out std_logic;
+
+		cur_state: out reset_state
+	);
+end component;
+
+--for por_0: power_on_reset use entity work.power_on_reset;
+
+signal clk: std_logic;
+signal reset: std_logic;
+signal core_en: std_logic;
+signal sys_clken: std_logic;
+signal cfg_drv: std_logic;
+signal rd_pmbrd_rev: std_logic;
+signal clk_33mhz_en: std_logic;
+signal current_state: reset_state;
+
+constant CLK50MHZ_period: time := 20 ns;  
+constant CLK33_period: time := 33 ns;
+constant LB_LCLK0_period: time := 16 ns; 
+
+begin
+
+	por_0: power_on_reset port map (
+		clk => clk,
+		reset => reset,
+
+		core_en => core_en,
+		sys_clken => sys_clken,
+		cfg_drv => cfg_drv,
+		rd_pmbrd_rev => rd_pmbrd_rev,
+
+		clk_33mhz_en => clk_33mhz_en,
+
+		cur_state => current_state
+	);
+
+
+CLK50MHZ_process :process
+begin
+	clk <= '0';
+	wait for CLK50MHZ_period/2;
+	clk <= '1';
+	wait for CLK50MHZ_period/2;
+end process;
+
+stim: process
+variable l: line;
+begin
+	report "asserting reset" severity note;
+	reset <= '1';
+
+	report "current_state is " & reset_state'image(current_state);
+	wait until current_state = reset_state'value("RST");	
+	report "saw state RST" severity note;
+	
+	wait for CLK50MHZ_period * 3;
+	report "de-asserting reset" severity note;
+	reset <= '0';
+
+	wait until core_en = '1';
+	report "saw core_en" severity note;
+
+	-- personality module id
+	wait until rd_pmbrd_rev = '1';
+	report "saw rd_pmbrd_rev assert" severity note;
+	wait until rd_pmbrd_rev = '0';
+	report "saw rd_pmbrd_rev de-assert" severity note;
+
+
+
+	wait for CLK50MHZ_period * 100;
+	report "end of test" severity note;
+	wait;
+end process;
+
+
+end behavior;
diff --git a/testsuite/gna/sr2676/reset.vhdl b/testsuite/gna/sr2676/reset.vhdl
new file mode 100644
index 0000000..7d1a33a
--- /dev/null
+++ b/testsuite/gna/sr2676/reset.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.reset_types.all;
+
+
+entity power_on_reset is
+	generic(
+		clk_period_ns: unsigned := X"14"
+	);
+	port (
+		clk: in std_logic;
+		reset: in std_logic;
+
+		core_en: out std_logic;
+		sys_clken: out std_logic;
+		clk_33mhz_en: out std_logic;
+		cfg_drv: out std_logic;
+		rd_pmbrd_rev : out std_logic;
+		
+
+		cur_state: out reset_state
+	);
+end power_on_reset;
+
diff --git a/testsuite/gna/sr2676/reset_types.vhdl b/testsuite/gna/sr2676/reset_types.vhdl
new file mode 100644
index 0000000..791e44f
--- /dev/null
+++ b/testsuite/gna/sr2676/reset_types.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+use ieee.numeric_std.all;
+package reset_types is
+
+type reset_state is (
+	RST,
+	ENABLE_CORE_POWER,
+	SAMPLE_HW_CONFIG,
+	SELECT_PROCESSOR_POR_CONFIG,
+	SELECT_PERSONALITY_ID,
+	SAMPLE_PERSONALITY_ID,
+	DESELECT_PERSONALITY_ID,
+	DEASSERT_HRESET,
+	DESELECT_PROCESSOR_POR_CONFIG,
+	WAIT_FOR_PROCESSOR,
+	ENABLE_ALL_DEVICES,
+	MONITOR_RESET
+);
+
+
+end reset_types;
diff --git a/testsuite/gna/sr2676/testsuite.sh b/testsuite/gna/sr2676/testsuite.sh
new file mode 100755
index 0000000..65632a2
--- /dev/null
+++ b/testsuite/gna/sr2676/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze reset_types.vhdl reset.vhdl reset-rtl.vhdl reset-test.vhdl
+elab_simulate reset_testbench --stop-time=1us
+
+clean
+
+echo "Test successful"