Import vests testsuite

15 files changed, 1158 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd
new file mode 100644
index 0000000..6398be1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/architectural.vhd
@@ -0,0 +1,37 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration architectural of computer_system is
+
+  for block_level
+
+    -- . . .    -- component configurations for cpu and memory, etc
+
+    for instrumentation
+
+      for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
+        use entity work.bus_monitor(general_purpose)
+        generic map ( verbose => true, dump_stats => true );
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration architectural;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd
new file mode 100644
index 0000000..faf4b2a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/carry_chain.vhd
@@ -0,0 +1,112 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity nmos is
+  port ( terminal gate, source, drain : electrical );
+end entity nmos;
+
+architecture ideal of nmos is
+begin
+end architecture ideal;
+
+architecture spice_equivalent of nmos is
+begin
+end architecture spice_equivalent;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity pmos is
+  port ( terminal gate, source, drain : electrical );
+end entity pmos;
+
+architecture ideal of pmos is
+begin
+end architecture ideal;
+
+
+
+-- code from book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity carry_chain is
+  generic ( n : positive );
+  port ( terminal clk, c_in, c_out, vdd, vss : electrical;
+         terminal p, g : electrical_vector (1 to n) );
+end entity carry_chain;
+
+----------------------------------------------------------------
+
+architecture device_level of carry_chain is
+
+  component nmos is
+    port ( terminal gate, source, drain : electrical );
+  end component nmos;
+
+  component pmos is
+    port ( terminal gate, source, drain : electrical );
+  end component pmos;
+
+  terminal c_neg : electrical_vector(0 to n-1);
+
+begin
+
+  bit_array : for index in 0 to n generate
+    terminal clk_pulldown_drain : electrical;
+  begin
+
+    clk_pulldown : component nmos
+      port map ( clk, vss, clk_pulldown_drain );
+
+    bit_0 : if index = 0 generate
+    begin
+      clk_precharge : component pmos
+        port map ( clk, c_neg(index), vdd );
+      g_pulldown : component nmos
+        port map ( c_in, clk_pulldown_drain, c_neg(index) );
+    end generate bit_0;
+
+    middle_bit : if index /= 0 and index /= n generate
+    begin
+      clk_precharge : component pmos
+        port map ( clk, c_neg(index), vdd );
+      g_pulldown : component nmos
+        port map ( g(index), clk_pulldown_drain, c_neg(index) );
+      p_pass : component nmos
+        port map ( p(index), c_neg(index - 1), c_neg(index) );
+    end generate middle_bit;
+
+    bit_n : if index = n generate
+    begin
+      clk_precharge : component pmos
+        port map ( clk, c_out, vdd );
+      g_pulldown : component nmos
+        port map ( g(index), clk_pulldown_drain, c_out );
+      p_pass : component nmos
+        port map ( p(index), c_neg(index - 1), c_out );
+    end generate bit_n;
+
+  end generate bit_array;
+
+end architecture device_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
new file mode 100644
index 0000000..972be8b
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system-1.vhd
@@ -0,0 +1,188 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package bus_monitor_pkg is
+
+  type stats_type is record
+      ifetch_freq, write_freq, read_freq : real;
+    end record stats_type;
+
+  component bus_monitor is
+    generic ( verbose, dump_stats : boolean := false );
+    port ( mem_req, ifetch, write : in bit;
+           bus_stats : out stats_type );
+  end component bus_monitor;
+
+end package bus_monitor_pkg;
+
+
+use work.bus_monitor_pkg.all;
+
+entity bus_monitor is
+  generic ( verbose, dump_stats : boolean := false );
+  port ( mem_req, ifetch, write : in bit;
+         bus_stats : out stats_type );
+end entity bus_monitor;
+
+
+architecture general_purpose of bus_monitor is
+begin
+
+  access_monitor : process is
+
+    variable access_count, ifetch_count,
+             write_count, read_count : natural := 0;
+      use std.textio;
+      variable L : textio.line;
+
+  begin
+    wait until mem_req = '1';
+    if ifetch = '1' then
+      ifetch_count := ifetch_count + 1;
+        if verbose then
+          textio.write(L, string'("Ifetch"));
+          textio.writeline(textio.output, L);
+        end if;
+    elsif write = '1' then
+      write_count := write_count + 1;
+        if verbose then
+          textio.write(L, string'("Write"));
+          textio.writeline(textio.output, L);
+        end if;
+    else
+      read_count := read_count + 1;
+        if verbose then
+          textio.write(L, string'("Read"));
+          textio.writeline(textio.output, L);
+        end if;
+    end if;
+    access_count := access_count + 1;
+    bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
+    bus_stats.write_freq <= real(write_count) / real(access_count);
+    bus_stats.read_freq <= real(read_count) / real(access_count);
+      if dump_stats and access_count mod 5 = 0 then
+        textio.write(L, string'("Ifetch frequency = "));
+        textio.write(L, real(ifetch_count) / real(access_count));
+        textio.writeline(textio.output, L);
+        textio.write(L, string'("Write frequency = "));
+        textio.write(L, real(write_count) / real(access_count));
+        textio.writeline(textio.output, L);
+        textio.write(L, string'("Read frequency = "));
+        textio.write(L, real(read_count) / real(access_count));
+        textio.writeline(textio.output, L);
+      end if;
+  end process access_monitor;
+
+end architecture general_purpose;
+
+
+
+-- code from book (in text)
+
+entity computer_system is
+  generic ( instrumented : boolean := false );
+  port ( -- . . . );
+  -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc.
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc.
+
+  instrumentation : if instrumented generate
+
+    use work.bus_monitor_pkg;
+    signal bus_stats : bus_monitor_pkg.stats_type;
+
+  begin
+
+    cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
+      port map ( mem_req, ifetch, write, bus_stats );
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
new file mode 100644
index 0000000..19a5efc
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/computer_system.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- code from book (in text)
+
+entity computer_system is
+  generic ( instrumented : boolean := false );
+  port ( -- . . . );
+  -- not in book
+         other_port : in bit := '0' );
+  -- end not in book
+end entity computer_system;
+
+-- end code from book
+
+
+-- code from book
+
+architecture block_level of computer_system is
+
+  -- . . .    -- type and component declarations for cpu and memory, etc
+
+  signal clock : bit;    -- the system clock
+  signal mem_req : bit;  -- cpu access request to memory
+  signal ifetch : bit;   -- indicates access is to fetch an instruction
+  signal write : bit;    -- indicates access is a write
+  -- . . .                  -- other signal declarations
+
+begin
+
+  -- . . .    -- component instances for cpu and memory, etc
+
+  instrumentation : if instrumented generate
+
+    signal ifetch_freq, write_freq, read_freq : real := 0.0;
+
+  begin
+
+    access_monitor : process is
+      variable access_count, ifetch_count,
+               write_count, read_count : natural := 0;
+    begin
+      wait until mem_req = '1';
+      if ifetch = '1' then
+        ifetch_count := ifetch_count + 1;
+      elsif write = '1' then
+        write_count := write_count + 1;
+      else
+        read_count := read_count + 1;
+      end if;
+      access_count := access_count + 1;
+      ifetch_freq <= real(ifetch_count) / real(access_count);
+      write_freq <= real(write_count) / real(access_count);
+      read_freq <= real(read_count) / real(access_count);
+    end process access_monitor;
+
+  end generate instrumentation;
+
+  -- not in book
+
+  stimulus : process is
+  begin
+    ifetch <= '1';  write <= '0';
+    mem_req <= '1', '0' after 10 ns;
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '1';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '1';  write <= '0';
+    wait for 20 ns;
+
+    mem_req <= '1', '0' after 10 ns;
+    ifetch <= '0';  write <= '0';
+    wait for 20 ns;
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture block_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd
new file mode 100644
index 0000000..a6c82e0
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/down_to_chips.vhd
@@ -0,0 +1,61 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity DRAM_4M_by_4 is
+  port ( a :  in std_logic_vector(0 to 10);
+         d :  inout std_logic_vector(0 to 3);
+         cs, we, ras, cas : in std_logic );
+end entity DRAM_4M_by_4;
+
+
+architecture chip_function of DRAM_4M_by_4 is
+begin
+  d <= (others => 'Z');
+end architecture chip_function;
+
+
+-- code from book
+
+library chip_lib;  use chip_lib.all;
+
+configuration down_to_chips of memory_board is
+
+  for chip_level
+
+    for bank_array
+
+      for nibble_array
+
+        for a_DRAM : DRAM
+          use entity DRAM_4M_by_4(chip_function);
+        end for;
+
+      end for;
+
+    end for;
+
+    -- . . .    -- configurations of other component instances
+
+  end for;
+
+end configuration down_to_chips;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd
new file mode 100644
index 0000000..4d0cfa8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/fanout_tree.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity buf is
+  port ( a : in std_logic;  y : out std_logic );
+end entity buf;
+
+
+architecture basic of buf is
+begin
+  y <= a;
+end architecture basic;
+
+
+
+
+-- code from book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity fanout_tree is
+  generic ( height : natural );
+  port ( input : in std_logic;
+         output : out std_logic_vector (0 to 2**height - 1) );
+end entity fanout_tree;
+
+--------------------------------------------------
+
+architecture recursive of fanout_tree is
+
+begin
+
+  degenerate_tree : if height = 0 generate
+  begin
+    output(0) <= input;
+  end generate degenerate_tree;
+
+  compound_tree : if height > 0 generate
+    signal buffered_input_0, buffered_input_1 : std_logic;
+  begin
+
+    buf_0 : entity work.buf(basic)
+      port map ( a => input, y => buffered_input_0 );
+
+    subtree_0 : entity work.fanout_tree(recursive)
+      generic map ( height => height - 1 )
+      port map ( input => buffered_input_0,
+                 output => output(0 to 2**(height - 1) - 1) );
+
+    buf_1 : entity work.buf(basic)
+      port map ( a => input, y => buffered_input_1 );
+
+    subtree_1 : entity work.fanout_tree(recursive)
+      generic map ( height => height - 1 )
+      port map ( input => buffered_input_1,
+                 output => output(2**(height - 1) to 2**height - 1) );
+
+  end generate compound_tree;
+
+end architecture recursive;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd
new file mode 100644
index 0000000..88b11ac
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/graphics_engine.vhd
@@ -0,0 +1,81 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+entity graphics_engine is
+end entity graphics_engine;
+
+-- end not in book
+
+
+architecture behavioral of graphics_engine is
+
+  type point is array (1 to 3) of real;
+  type transformation_matrix is array (1 to 3, 1 to 3) of real;
+
+  signal p, transformed_p : point;
+  signal a : transformation_matrix;
+  signal clock : bit;
+  -- . . .
+
+begin
+
+  transform_stage : for i in 1 to 3 generate
+  begin
+
+    cross_product_transform : process is
+      variable result1, result2, result3 : real := 0.0;
+    begin
+      wait until clock = '1';
+      transformed_p(i) <= result3;
+      result3 := result2;
+      result2 := result1;
+      result1 :=  a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
+    end process cross_product_transform;
+
+  end generate transform_stage;
+
+  -- . . .    -- other stages in the pipeline, etc
+
+  -- not in book
+
+  clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
+
+  stimulus : process is
+  begin
+    a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
+    p <= ( 10.0, 10.0, 10.0 );
+    wait until clock = '0';
+    p <= ( 20.0, 20.0, 20.0 );
+    wait until clock = '0';
+    p <= ( 30.0, 30.0, 30.0 );
+    wait until clock = '0';
+    p <= ( 40.0, 40.0, 40.0 );
+    wait until clock = '0';
+    p <= ( 50.0, 50.0, 50.0 );
+    wait until clock = '0';
+    p <= ( 60.0, 60.0, 60.0 );
+
+    wait;
+  end process stimulus;
+
+  -- end not in book
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd
new file mode 100644
index 0000000..2e9e460
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/identical_devices.vhd
@@ -0,0 +1,40 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library device_lib;
+
+configuration identical_devices of led_bar_display is
+
+  for device_level
+
+    for device_array
+
+      for limiting_resistor : resistor
+        use entity device_lib.resistor(ideal);
+      end for;
+
+      for segment_led : led
+        use entity device_lib.led(ideal);
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration identical_devices;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt
new file mode 100644
index 0000000..bfbcd59
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/index-ams.txt
@@ -0,0 +1,33 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                         Chapter 17 - Generate Statements
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+led_bar_display.vhd                             entity resistor                         ideal                           --
+--                                              entity led                              ideal                           --
+--                                              entity led_bar_display                  device_level                    Figure 17-2
+resistor_pack.vhd                               entity resistor_pack                    coupled                         Figure 17-3
+graphics_engine.vhd                             entity graphics_engine                  behavioral                      Figure 17-4
+memory_board.vhd                                entity DRAM                             empty                           --
+--                                              entity memory_board                     chip_level                      Figure 17-5
+carry_chain.vhd                                 entity nmos                             ideal, spice_equivalent         --
+--                                              entity carry_chain                      device_level                    Figure 17-8
+computer_system.vhd                             entity computer_system                  block_level                     Section 17.2, Figure 17-9
+fanout_tree.vhd                                 entity buf                              basic                           --
+--                                              entity fanout_tree                      recursive                       Figure 17-11
+computer_system-1.vhd                           package bus_monitor_pkg                 --                              --
+--                                              entity bus_monitor                      general_purpose                 --
+--                                              entity computer_system                  block_level                     Figure 17-12
+architectural.vhd                               configuration architectural             --                              Figure 17-13
+identical_devices.vhd                           configuration identical_devices         --                              Figure 17-14
+down_to_chips.vhd                               entity DRAM_4M_by_4                     chip_function                   --
+--                                              configuration down_to_chips             --                              Figure 17-15
+last_pass_spice.vhd                             configuration last_pass_spice           --                              Figure 17-16
+inline_01.vhd                                   entity inline_01                        test                            --
+--                                              configuration inline_01_test            --                              Section 17.2
+inline_02.vhd                                   entity inline_02                        test                            Section 17.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd
new file mode 100644
index 0000000..61342d7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_01.vhd
@@ -0,0 +1,58 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+end entity inline_01;
+
+
+architecture test of inline_01 is
+
+  component computer_system is
+    port ( other_port : in bit := '0' );
+  end component computer_system;
+
+begin
+
+  system_under_test : component computer_system
+    port map ( other_port => open );
+
+end architecture test;
+
+
+
+configuration inline_01_test of inline_01 is
+
+  for test
+
+    -- code from book (in text)
+
+    for system_under_test : computer_system
+      use entity work.computer_system(block_level)
+      generic map ( instrumented => true )
+      -- . . .
+      -- not in book
+      ;
+      -- end not in book
+    end for;
+
+    -- end code from book
+
+  end for;
+
+end configuration inline_01_test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd
new file mode 100644
index 0000000..b6f9aba
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/inline_02.vhd
@@ -0,0 +1,48 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity inline_02 is
+end entity inline_02;
+
+
+architecture test of inline_02 is
+
+  signal unbuffered_clock : std_logic;
+  signal buffered_clock_array : std_logic_vector(0 to 7);
+
+begin
+
+  -- code from book (in text)
+
+  clock_buffer_tree : entity work.fanout_tree(recursive)
+    generic map ( height => 3 )
+    port map ( input => unbuffered_clock,
+               output => buffered_clock_array );
+
+  -- end code from book
+
+  clock_gen : process is
+  begin
+    unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
+    wait for 10 ns;
+  end process clock_gen;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd
new file mode 100644
index 0000000..dae9ff2
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/last_pass_spice.vhd
@@ -0,0 +1,66 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library device_lib;
+
+configuration last_pass_spice of carry_chain is
+
+  for device_level
+
+    for bit_array ( 0 to n - 1 )
+
+      for bit_0
+        for all : nmos
+          use entity device_lib.nmos(ideal);
+        end for;
+        for all : pmos
+          use entity device_lib.pmos(ideal);
+        end for;
+      end for;
+
+      for middle_bit
+        for all : nmos
+          use entity device_lib.nmos(ideal);
+        end for;
+        for all : pmos
+          use entity device_lib.pmos(ideal);
+        end for;
+      end for;
+
+    end for;
+
+    for bit_array ( n )
+
+      for bit_n
+        for p_pass : nmos
+          use entity device_lib.nmos(spice_equivalent);
+        end for;
+        for others : nmos
+          use entity device_lib.nmos(ideal);
+        end for;
+        for all : pmos
+          use entity device_lib.pmos(ideal);
+        end for;
+      end for;
+
+    end for;
+
+  end for;
+
+end configuration last_pass_spice;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd
new file mode 100644
index 0000000..d17e5a1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/led_bar_display.vhd
@@ -0,0 +1,85 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- analyze into resource library device_lib
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity resistor is
+  port ( terminal p1, p2 : electrical );
+end entity resistor;
+
+architecture ideal of resistor is
+begin
+end architecture ideal;
+
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity led is
+  port ( terminal anode, cathode : electrical );
+end entity led;
+
+architecture ideal of led is
+begin
+end architecture ideal;
+
+
+
+-- code from book
+
+library ieee_proposed;  use ieee_proposed.electrical_systems.all;
+
+entity led_bar_display is
+  generic ( width : positive );
+  port ( terminal anodes : electrical_vector(1 to width);
+         terminal common_cathode : electrical );
+end entity led_bar_display;
+
+----------------------------------------------------------------
+
+architecture device_level of led_bar_display is
+
+  component resistor is
+    port ( terminal p1, p2 : electrical );
+  end component resistor;
+
+  component led is
+    port ( terminal anode, cathode : electrical );
+  end component led;
+
+begin
+
+  device_array : for segment in 1 to width generate
+
+    terminal led_anode : electrical;
+
+  begin
+
+    limiting_resistor : component resistor
+      port map ( p1 => anodes(segment), p2 => led_anode );
+
+    segment_led : component led
+      port map ( anode => led_anode, cathode => common_cathode );
+
+  end generate device_array;
+
+end architecture device_level;
+
+-- end code from book
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd
new file mode 100644
index 0000000..65a35f1
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd
@@ -0,0 +1,94 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- not in book
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity DRAM is
+  port ( a :  in std_logic_vector(0 to 10);
+         d :  inout std_logic_vector(0 to 3);
+         cs, we, ras, cas : in std_logic );
+end entity DRAM;
+
+
+architecture empty of DRAM is
+begin
+  d <= (others => 'Z');
+end architecture empty;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity memory_board is
+end entity memory_board;
+
+-- end not in book
+
+
+architecture chip_level of memory_board is
+
+  component DRAM is
+    port ( a :  in std_logic_vector(0 to 10);
+           d :  inout std_logic_vector(0 to 3);
+           cs, we, ras, cas : in std_logic );
+  end component DRAM;
+
+  signal buffered_address : std_logic_vector(0 to 10);
+  signal DRAM_data : std_logic_vector(0 to 31);
+  signal bank_select : std_logic_vector(0 to 3);
+  signal buffered_we, buffered_ras, buffered_cas : std_logic;
+
+  -- . . .    -- other declarations
+
+begin
+
+  bank_array : for bank_index in 0 to 3 generate
+  begin
+
+    nibble_array : for nibble_index in 0 to 7 generate
+
+      constant data_lo : natural := nibble_index * 4;
+      constant data_hi : natural := nibble_index * 4 + 3;
+
+    begin
+
+      a_DRAM : component DRAM
+        port map ( a => buffered_address,
+                   d => DRAM_data(data_lo to data_hi),
+                   cs => bank_select(bank_index),
+                   we => buffered_we,
+                   ras => buffered_ras,
+                   cas => buffered_cas );
+
+    end generate nibble_array;
+
+  end generate bank_array;
+
+  -- . . .    -- other component instances, etc
+
+  -- not in book
+
+  buffered_address <= "01010101010";
+  DRAM_data <= X"01234567";
+
+  -- end not in book
+
+end architecture chip_level;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd
new file mode 100644
index 0000000..42dec93
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/generators/resistor_pack.vhd
@@ -0,0 +1,49 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee_proposed;
+use ieee_proposed.electrical_systems.all, ieee_proposed.thermal_systems.all;
+
+entity resistor_pack is
+  generic ( resistances_at_298K : real_vector;
+            temperature_coeff : real := 0.0 );
+  port ( terminal p1, p2 : electrical_vector(1 to resistances_at_298K'length);
+         quantity package_temp : in temperature );
+end entity resistor_pack;
+
+----------------------------------------------------------------
+
+architecture coupled of resistor_pack is
+
+  quantity v across i through p1 to p2;
+  quantity effective_resistance : real_vector(1 to resistances_at_298K'length);
+
+begin
+
+  resistor_array : for index in 1 to resistances_at_298K'length generate
+
+    effective_resistance(index)
+      == resistances_at_298K(index)
+          + ( package_temp - 298.0 ) * temperature_coeff;
+
+    v(index ) == i(index) * effective_resistance(index);
+
+  end generate resistor_array;
+
+end architecture coupled;