Import vests testsuite

22 files changed, 1936 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd
new file mode 100644
index 0000000..59c5d45
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/CPU.vhd
@@ -0,0 +1,109 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.numeric_bit.all;
+
+package CPU_types is
+
+  subtype word is unsigned(0 to 31);
+  subtype byte is unsigned(0 to 7);
+
+  alias convert_to_natural is
+    to_integer [ unsigned return natural ];
+
+  constant halt_opcode : byte := "00000000";
+
+  type code_array is array (natural range <>) of word;
+  constant code : code_array := ( X"01000000", X"01000000", X"02000000",
+				  X"01000000", X"01000000", X"02000000",
+				  X"00000000" );
+
+end package CPU_types;
+
+
+
+use work.CPU_types.all;
+
+entity CPU is
+end entity CPU;
+
+
+-- code from book
+
+architecture instrumented of CPU is
+
+  type count_file is file of natural;
+  file instruction_counts : count_file open write_mode is "instructions";
+
+begin
+
+  interpreter : process is
+
+    variable IR : word;
+    alias opcode : byte is IR(0 to 7);
+    variable opcode_number : natural;
+    type counter_array is array (0 to 2**opcode'length - 1) of natural;
+    variable counters : counter_array := (others => 0);
+    -- . . .
+
+    -- not in book
+    variable code_index : natural := 0;
+    -- end not in book
+
+  begin
+
+    -- . . .    -- initialize the instruction set interpreter
+
+    instruction_loop : loop
+
+      -- . . .    -- fetch the next instruction into IR
+
+      -- not in book
+      IR := code(code_index);
+      code_index := code_index + 1;
+      -- end not in book
+
+      -- decode the instruction
+      opcode_number := convert_to_natural(opcode);
+      counters(opcode_number) := counters(opcode_number) + 1;
+      -- . . .
+
+      -- execute the decoded instruction
+      case opcode is
+        -- . . .
+        when halt_opcode => exit instruction_loop;
+        -- . . .
+        -- not in book
+        when others => null;
+        -- end not in book
+      end case;
+
+    end loop instruction_loop;
+
+    for index in counters'range loop
+      write(instruction_counts, counters(index));
+    end loop;
+    wait;  -- program finished, wait forever
+
+  end process interpreter;
+
+end architecture instrumented;
+
+-- code from book
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd
new file mode 100644
index 0000000..8d033db
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/ROM.vhd
@@ -0,0 +1,63 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity ROM is
+  generic ( load_file_name : string );
+  port ( sel : in std_logic;
+         address : in std_logic_vector;
+         data : inout std_logic_vector );
+end entity ROM;
+
+--------------------------------------------------
+
+architecture behavioral of ROM is
+
+begin
+
+  behavior : process is
+
+    subtype word is std_logic_vector(0 to data'length - 1);
+    type storage_array is
+      array (natural range 0 to 2**address'length - 1) of word;
+    variable storage : storage_array;
+    variable index : natural;
+    -- . . .    -- other declarations
+
+    type load_file_type is file of word;
+    file load_file : load_file_type open read_mode is load_file_name;
+
+  begin
+
+    -- load ROM contents from load_file
+    index := 0;
+    while not endfile(load_file) loop
+      read(load_file, storage(index));
+      index := index + 1;
+    end loop;
+
+    -- respond to ROM accesses
+    loop
+      -- . . .
+    end loop;
+
+  end process behavior;
+
+end architecture behavioral;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
new file mode 100644
index 0000000..df3116c
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/bus_monitor.vhd
@@ -0,0 +1,126 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity bus_monitor is
+end entity bus_monitor;
+
+
+
+architecture test of bus_monitor is
+
+  subtype byte is bit_vector(7 downto 0);
+  type byte_array is array (natural range <>) of byte;
+
+  function resolve_bytes ( drivers : in byte_array ) return byte is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bytes;
+
+  function resolve_bits ( drivers : in bit_vector ) return bit is
+  begin
+    return drivers(drivers'left);
+  end function resolve_bits;
+
+  -- code from book (in text)
+
+  signal address : bit_vector(15 downto 0);
+  signal data : resolve_bytes byte;
+  signal rd, wr, io : bit;    -- read, write, io/mem select
+  signal ready : resolve_bits bit;
+
+  -- end code from book
+
+begin
+
+-- code from book
+
+bus_monitor : process is
+
+  constant header : string(1 to 44)
+    := FF & "      Time   R/W I/M  Address          Data";
+
+  use std.textio.all;
+
+  file log : text open write_mode is "buslog";
+  variable trace_line : line;
+  variable line_count : natural := 0;
+
+begin
+
+  if line_count mod 60 = 0 then
+    write ( trace_line, header );
+    writeline ( log, trace_line );
+    writeline ( log, trace_line );    -- empty line
+  end if;
+  wait until (rd = '1' or wr = '1') and ready = '1';
+  write ( trace_line, now, justified => right, field => 10, unit => us );
+  write ( trace_line, string'("    ") );
+  if rd = '1' then
+    write ( trace_line, 'R' );
+  else
+    write ( trace_line, 'W' );
+  end if;
+  write ( trace_line, string'("   ") );
+  if io = '1' then
+    write ( trace_line, 'I' );
+  else
+    write ( trace_line, 'M' );
+  end if;
+  write ( trace_line, string'("   ") );
+  write ( trace_line, address );
+  write ( trace_line, ' ');
+  write ( trace_line, data );
+  writeline ( log, trace_line );
+  line_count := line_count + 1;
+
+end process bus_monitor;
+
+-- end code from book
+
+  stimulus : process is
+  begin
+    wait for 0.4 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0000";
+    data <= B"10011110";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 0.9 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0001";
+    data <= B"00010010";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.0 us - now;
+    rd <= '1', '0' after 10 ns;
+    address <= X"0014";
+    data <= B"11100111";
+    ready <= '1', '0' after 10 ns;
+
+    wait for 2.7 us - now;
+    wr <= '1', '0' after 10 ns;
+    io <= '1', '0' after 10 ns;
+    address <= X"0007";
+    data <= X"00";
+    ready <= '1', '0' after 10 ns;
+
+    wait;
+  end process stimulus;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd
new file mode 100644
index 0000000..b357670
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/cache.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity cache is
+  generic ( cache_size, block_size, associativity : positive;
+            benchmark_name : string(1 to 10) );
+  port ( halt : in bit );
+end entity cache;
+
+
+
+architecture instrumented of cache is
+
+begin
+
+  -- code from book
+
+  cache_monitor : process is
+
+    type measurement_record is
+      record
+        cache_size, block_size, associativity : positive;
+        benchmark_name : string(1 to 10);
+        miss_rate : real;
+        ave_access_time : delay_length;
+      end record;
+    type measurement_file is file of measurement_record;
+    file measurements : measurement_file
+      open append_mode is "cache-measurements";
+    -- . . .
+
+    -- not in book
+    constant miss_count : natural := 100;
+    constant total_accesses : natural := 1000;
+    constant total_delay : delay_length := 2400 ns;
+    -- end not in book
+
+  begin
+    -- . . .
+    loop
+      -- . . .
+      -- not in book
+      wait on halt;
+      -- end not in book
+      exit when halt = '1';
+      -- . . .
+    end loop;
+
+    write ( measurements,
+            measurement_record'(
+              -- write values of generics for this run
+              cache_size, block_size, associativity, benchmark_name,
+              -- calculate performance metrics
+              miss_rate => real(miss_count) / real(total_accesses),
+              ave_access_time => total_delay / total_accesses ) );
+    wait;
+
+  end process cache_monitor;
+
+  -- end code from book
+
+end architecture instrumented;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt
new file mode 100644
index 0000000..2a5e797
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/index-ams.txt
@@ -0,0 +1,38 @@
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                       Chapter 21 - Files and Input/Output
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Figure/Section
+-----------                                     ------------                            --------------                  --------------
+ROM.vhd                                         entity ROM                              behavioral                      Figure 21-1
+stimulate_network.vhd                           entity stimulate_network_write_data     writer                          --
+--                                              entity stimulate_network                test                            Figure 21-2
+CPU.vhd                                         package CPU_types                       --                              --
+--                                              entity CPU                              instrumented                    Figure 21-3
+cache.vhd                                       entity cache                            instrumented                    Figure 21-4
+read_array.vhd                                  entity read_array_write_data            writer                          --
+--                                              entity read_array                       test                            Section 21.1, Figure 21-5
+stimulus_generator.vhd                          entity stimulus_generator               test                            Figure 21-6
+read_transform.vhd                              entity read_transform_write_data        writer                          --
+--                                              entity read_transform                   test                            Section 21.1, Figure 21-7
+textio.vhd                                      package textio                          --                              Figure 21-8
+stimulus_interpreter-1.vhd                      entity stimulus_interpreter             test                            Figure 21-9
+bus_monitor.vhd                                 entity bus_monitor                      test                            Figure 21-10
+inline_01.vhd                                   entity inline_01                        test                            Section 21.1
+inline_02.vhd                                   entity inline_02_write_data             writer                          --
+--                                              entity inline_02                        test                            Section 21.1
+inline_03.vhd                                   entity inline_03                        test                            Section 21.1
+inline_04.vhd                                   entity inline_04                        test                            Section 21.1
+inline_05.vhd                                   entity inline_05                        test                            Section 21.1
+inline_06.vhd                                   entity inline_06                        test                            Section 21.1
+inline_08.vhd                                   entity inline_08                        test                            Section 21.2
+inline_09.vhd                                   entity inline_09                        test                            Section 21.2
+inline_10.vhd                                   entity inline_10                        test                            Section 21.2
+---------------------------------------------------------------------------------------------------------------------------------------------
+--                                                                    TestBenches
+---------------------------------------------------------------------------------------------------------------------------------------------
+-- Filename                                     Primary Unit                            Secondary Unit                  Tested Model
+------------                                    ------------                            --------------                  ------------
+tb_ROM.vhd                                      entity tb_ROM_write_data                writer                          --
+--                                              entity tb_ROM                           test                            ROM.vhd
+tb_cache.vhd                                    entity tb_cache                         test                            cache.vhd
+--                                              entity tb_cache_read_data               reader                          --
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd
new file mode 100644
index 0000000..3b7bf15
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_01.vhd
@@ -0,0 +1,87 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_01 is
+
+end entity inline_01;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_01 is
+begin
+
+
+  process is
+
+    -- code from book:
+
+    type integer_file is file of integer;
+
+    file lookup_table_file : integer_file is "lookup-values";
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    -- code from book:
+
+    type file_open_kind is (read_mode, write_mode, append_mode);
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+
+    -- code from book:
+
+    type file_type is file of element_type;
+
+    procedure read ( file f : file_type;  value : out element_type );
+
+    function endfile ( file f : file_type ) return boolean;
+
+    -- end of code from book
+
+    procedure read ( file f : file_type;  value : out element_type ) is
+    begin
+    end;
+
+    function endfile ( file f : file_type ) return boolean is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd
new file mode 100644
index 0000000..f31a157
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_02.vhd
@@ -0,0 +1,124 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_02_write_data is
+end entity inline_02_write_data;
+
+
+architecture writer of inline_02_write_data is
+begin
+
+  process is
+    type bit_vector_file is file of bit_vector;
+    file vectors : bit_vector_file open write_mode is "vectors.dat";
+  begin
+    write(vectors, bit_vector'(""));
+    write(vectors, bit_vector'("1"));
+    write(vectors, bit_vector'("10"));
+    write(vectors, bit_vector'("011"));
+    write(vectors, bit_vector'("0100"));
+    write(vectors, bit_vector'("00101"));
+    write(vectors, bit_vector'("000110"));
+    write(vectors, bit_vector'("0000111"));
+    write(vectors, bit_vector'("00001000"));
+    write(vectors, bit_vector'("111111111111111111111111111111111111111111111111111111111111111111111111"));
+    wait;
+  end process;
+
+end architecture writer;
+
+
+----------------------------------------------------------------
+
+
+
+entity inline_02 is
+
+end entity inline_02;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_02 is
+begin
+
+
+  process is
+
+   type element_type is (t1, t2, t3);
+   type file_type is file of element_type;
+
+    -- code from book:
+
+    type bit_vector_file is file of bit_vector;
+
+    procedure read ( file f : file_type;
+                     value : out element_type;  length : out natural );
+
+    -- end of code from book
+
+    procedure read ( file f : file_type;
+                     value : out element_type;  length : out natural ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    type bit_vector_file is file of bit_vector;
+
+    -- code from book:
+
+    file vectors : bit_vector_file open read_mode is "vectors.dat";
+    variable next_vector : bit_vector(63 downto 0);
+    variable actual_len : natural;
+
+    -- end of code from book
+
+    variable lost : boolean;
+
+  begin
+    while not endfile(vectors) loop
+
+      -- code from book:
+
+      read(vectors, next_vector, actual_len);
+
+      -- end of code from book
+
+      lost :=
+      -- code from book:
+
+      actual_len > next_vector'length
+
+      -- end of code from book
+      ;
+
+    end loop;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd
new file mode 100644
index 0000000..3813e24
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_03.vhd
@@ -0,0 +1,53 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_03 is
+
+end entity inline_03;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_03 is
+begin
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+
+    type file_type is file of element_type;
+
+    -- code from book:
+
+    procedure write ( file f : file_type;  value : in element_type );
+
+    -- end of code from book
+
+    procedure write ( file f : file_type;  value : in element_type ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd
new file mode 100644
index 0000000..725af8a
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_04.vhd
@@ -0,0 +1,62 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_04 is
+
+end entity inline_04;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_04 is
+begin
+
+
+  process is
+
+    type data_file_type is file of character;
+    variable ch : character;
+
+    -- code from book:
+
+    procedure write_to_file is
+      file data_file : data_file_type open write_mode is "datafile";
+    begin
+      -- . . .
+      -- not in book
+      write(data_file, ch);
+      -- end not in book
+    end procedure write_to_file;
+
+    -- end of code from book
+
+  begin
+    ch := 'A';
+    write_to_file;
+    ch := 'B';
+    write_to_file;
+    ch := 'C';
+    write_to_file;
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd
new file mode 100644
index 0000000..bcbe6bd
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_05.vhd
@@ -0,0 +1,59 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_05 is
+
+end entity inline_05;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_05 is
+
+  type log_file is file of string;
+
+  -- code from book:
+
+  file log_info : log_file open write_mode is "logfile";
+
+  -- end of code from book
+
+begin
+
+
+  process is
+  begin
+    write(log_info, string'("AAAA"));
+    wait for 1 ns;
+    write(log_info, string'("BBBB"));
+    wait;
+  end process;
+
+
+  process is
+  begin
+    write(log_info, string'("CCCC"));
+    wait for 1 ns;
+    write(log_info, string'("DDDD"));
+    wait;
+  end process;
+
+
+end architecture test;	  
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
new file mode 100644
index 0000000..2086041
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_06.vhd
@@ -0,0 +1,142 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_06 is
+
+end entity inline_06;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_06 is
+
+  type integer_file is file of integer;
+
+begin
+
+
+  process is
+
+    -- code from book:
+
+    file lookup_table_file, result_file : integer_file;
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+
+    -- code from book:
+
+    type file_type is file of element_type;
+
+    procedure file_open ( file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode );
+
+    -- end of code from book
+
+    procedure file_open ( file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    -- code from book:
+
+    file lookup_table_file : integer_file open read_mode is "lookup-values";
+
+    -- end of code from book
+
+  begin
+    wait;
+  end process;
+
+
+  process is
+
+    -- code from book:
+
+    file lookup_table_file : integer_file;
+    -- . . .
+
+    -- end of code from book
+
+  begin
+
+    -- code from book:
+
+    file_open ( lookup_table_file,
+                external_name => "lookup-values", open_kind => read_mode );
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+  process is
+
+    type element_type is (t1, t2, t3);
+    type file_type is file of element_type;
+
+    -- code from book:
+
+    type file_open_status is (open_ok, status_error, name_error, mode_error);
+
+    procedure file_open ( status : out file_open_status;
+                          file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode );
+
+    procedure file_close ( file f : file_type );
+
+    -- end of code from book
+
+    procedure file_open ( status : out file_open_status;
+                          file f : file_type;
+                          external_name : in string;
+                          open_kind : in file_open_kind := read_mode ) is
+    begin
+    end;
+
+    procedure file_close ( file f : file_type ) is
+    begin
+    end;
+
+  begin
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd
new file mode 100644
index 0000000..e43c83f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_08.vhd
@@ -0,0 +1,80 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_08 is
+
+end entity inline_08;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_08 is
+begin
+
+
+  process is
+
+    use std.textio.all;
+    file f : text open read_mode is "inline_08.dat";
+    variable L : line;
+    variable ch : character;
+    variable s : string(1 to 5);
+    variable i : integer;
+    variable r : real;
+
+  begin
+
+    readline(f, L);
+    read(L, ch);
+    report character'image(ch);
+    read(L, ch);
+    report character'image(ch);
+
+    readline(f, L);
+    read(L, s);
+    report '"' & s & '"';
+    read(L, s);
+    report '"' & s & '"';
+
+    readline(f, L);
+
+    -- code from book:
+
+    if L'length < s'length then
+      read(L, s(1 to L'length));
+    else
+      read(L, s);
+    end if;
+
+    -- end of code from book
+
+    report '"' & s & '"';
+
+    readline(f, L);
+    read(L, i);
+    report integer'image(i);
+    read(L, r);
+    report real'image(r);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
new file mode 100644
index 0000000..f2cccc4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_09.vhd
@@ -0,0 +1,70 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_09 is
+
+end entity inline_09;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_09 is
+begin
+
+
+  process is
+
+    use std.textio.all;
+    variable L : line;
+
+  begin
+
+    write(L, 42, justified => left, field => 5);
+    writeline(output, L);
+    write(L, 42, justified => right, field => 5);
+    writeline(output, L);
+    write(L, 123, field => 2);
+    writeline(output, L);
+
+    -- code from book:
+
+    write ( L, string'( "fred" ) );
+    write ( L, ' ' );
+    write ( L, bit_vector'( X"3A" ) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    write(L, 3.14159, digits => 2);
+    writeline(output, L);
+    write(L, 123.4567, digits => 0);
+    writeline(output, L);
+
+    write(L, 40 ns, unit => ps);
+    writeline(output, L);
+    write(L, 23 us, unit => ms);
+    writeline(output, L);
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
new file mode 100644
index 0000000..059075f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/inline_10.vhd
@@ -0,0 +1,77 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity inline_10 is
+
+end entity inline_10;
+
+
+----------------------------------------------------------------
+
+
+architecture test of inline_10 is
+begin
+
+
+  process is
+
+    use std.textio.all;
+    variable L : line;
+
+    -- code from book:
+
+    type speed_category is (stopped, slow, fast, maniacal);
+    variable speed : speed_category;
+
+    -- end of code from book
+
+  begin
+
+    speed := stopped;
+
+    -- code from book:
+
+    write ( L, speed_category'image(speed) );
+
+    -- end of code from book
+
+    writeline(output, L);
+
+    speed := slow;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := fast;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+    speed := maniacal;
+    write ( L, speed_category'image(speed) );
+    writeline(output, L);
+
+    -- code from book:
+
+    readline( input, L );
+    speed := speed_category'value(L.all);
+
+    -- end of code from book
+
+    wait;
+  end process;
+
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
new file mode 100644
index 0000000..dbec796
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_array.vhd
@@ -0,0 +1,104 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity read_array_write_data is
+end entity read_array_write_data;
+
+
+architecture writer of read_array_write_data is
+begin
+
+  process is
+
+    type integer_file is file of integer;
+    file data_file : integer_file open write_mode is "coeff-data";
+
+  begin
+    write(data_file, 0);
+    write(data_file, 1);
+    write(data_file, 2);
+    write(data_file, 3);
+    write(data_file, 4);
+    write(data_file, 5);
+    write(data_file, 6);
+    write(data_file, 7);
+    write(data_file, 8);
+    write(data_file, 9);
+    write(data_file, 10);
+    write(data_file, 11);
+    write(data_file, 12);
+    write(data_file, 13);
+    write(data_file, 14);
+    write(data_file, 15);
+    write(data_file, 16);
+    write(data_file, 17);
+    write(data_file, 18);
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity read_array is
+end entity read_array;
+
+
+architecture test of read_array is
+begin
+
+  process is
+
+    -- code from book (in text)
+
+    type integer_vector is array (integer range <>) of integer;
+
+    -- end code from book
+
+    -- code from book (in Figure)
+
+    impure function read_array ( file_name : string;  array_length : natural )
+                               return integer_vector is
+      type integer_file is file of integer;
+      file data_file : integer_file open read_mode is file_name;
+      variable result : integer_vector(1 to array_length) := (others => 0);
+      variable index : integer := 1;
+    begin
+      while not endfile(data_file) and index <= array_length loop
+        read(data_file, result(index));
+        index := index + 1;
+      end loop;
+      return result;
+    end function read_array;
+
+    -- end code from book
+
+    -- code from book (in text)
+
+    constant coeffs : integer_vector := read_array("coeff-data", 16);
+
+    -- end code from book
+
+  begin
+    wait;
+  end process;
+
+end architecture test;
+
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd
new file mode 100644
index 0000000..74f1d72
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/read_transform.vhd
@@ -0,0 +1,93 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity read_transform_write_data is
+end entity read_transform_write_data;
+
+
+architecture writer of read_transform_write_data is
+begin
+
+  process is
+    type transform_file is file of real;
+    file initial_transforms : transform_file open write_mode is "transforms.ini";
+  begin
+    for i in 1 to 50 loop
+      write(initial_transforms, real(i));
+    end loop;
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+
+entity read_transform is
+end entity read_transform;
+
+
+architecture test of read_transform is
+begin
+
+  process is
+
+    -- code from book (in text)
+
+    type transform_array is array (1 to 3, 1 to 3) of real;
+    variable transform1, transform2 : transform_array;
+
+    type transform_file is file of real;
+    file initial_transforms : transform_file open read_mode is "transforms.ini";
+
+    -- end code from book
+
+    -- code from book (in Figure)
+
+    procedure read_transform ( file f : transform_file;
+                               variable transform : out transform_array ) is
+    begin
+      for i in transform'range(1) loop
+        for j in transform'range(2) loop
+          if endfile(f) then
+            report "unexpected end of file in read_transform - "
+                   & "some array elements not read"
+              severity error;
+            return;
+          end if;
+          read ( f, transform(i, j) );
+        end loop;
+      end loop;
+    end procedure read_transform;
+
+    -- end code from book
+
+  begin
+
+    -- code from book (in text)
+
+    read_transform ( initial_transforms, transform1 );
+    read_transform ( initial_transforms, transform2 );
+
+    -- end code from book
+
+    wait;
+  end process;
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd
new file mode 100644
index 0000000..a7e7184
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulate_network.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity stimulate_network_write_data is
+end entity stimulate_network_write_data;
+
+
+architecture writer of stimulate_network_write_data is
+begin
+
+  process is
+    type packet_file is file of bit_vector;
+    file stimulus_file : packet_file open write_mode is "test packets";
+  begin
+    write(stimulus_file, X"6C");
+    write(stimulus_file, X"05");
+    write(stimulus_file, X"3");
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+entity stimulate_network is
+end entity stimulate_network;
+
+
+architecture test of stimulate_network is
+
+  signal stimulus_network, stimulus_clock : bit;
+
+begin
+
+  clock_gen : stimulus_clock <= not stimulus_clock after 10 ns;
+
+  -- code from book
+
+  stimulate_network : process is
+
+    type packet_file is file of bit_vector;
+    file stimulus_file : packet_file open read_mode is "test packets";
+
+    -- variable packet : bit_vector(1 to 2048);
+    -- not in book (for testing only)
+    variable packet : bit_vector(1 to 8);
+    -- end not in book
+    variable packet_length : natural;
+
+  begin
+
+    while not endfile(stimulus_file) loop
+
+      read(stimulus_file, packet, packet_length);
+      if packet_length > packet'length then
+        report "stimulus packet too long - ignored" severity warning;
+      else
+        for bit_index in 1 to packet_length loop
+          wait until stimulus_clock = '1';
+          stimulus_network <= not stimulus_network;
+          wait until stimulus_clock = '0';
+          stimulus_network <= stimulus_network xor packet(bit_index);
+        end loop;
+      end if;
+
+    end loop;
+
+    wait;  -- end of stimulation: wait forever
+
+  end process stimulate_network;
+
+  -- code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd
new file mode 100644
index 0000000..0393ff7
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_generator.vhd
@@ -0,0 +1,75 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity stimulus_generator is
+end entity stimulus_generator;
+
+
+architecture test of stimulus_generator is
+
+
+
+begin
+
+  -- code from book
+
+  stimulus_generator : process is
+
+    type directory_file is file of string;
+    file directory : directory_file open read_mode is "stimulus-directory";
+    variable file_name : string(1 to 50);
+    variable file_name_length : natural;
+    variable open_status : file_open_status;
+
+    subtype stimulus_vector is std_logic_vector(0 to 9);
+    type stimulus_file is file of stimulus_vector;
+    file stimuli : stimulus_file;
+    variable current_stimulus : stimulus_vector;
+    -- . . .
+
+  begin
+    file_loop : while not endfile(directory) loop
+      read( directory, file_name, file_name_length );
+      if file_name_length > file_name'length then
+        report "file name too long: " & file_name & "... - file skipped"
+          severity warning;
+        next file_loop;
+      end if;
+      file_open ( open_status, stimuli,
+                  file_name(1 to file_name_length), read_mode );
+      if open_status /= open_ok then
+        report file_open_status'image(open_status) & " while opening file "
+               & file_name(1 to file_name_length) & " - file skipped"
+          severity warning;
+        next file_loop;
+      end if;
+      stimulus_loop : while not endfile(stimuli) loop
+        read(stimuli, current_stimulus);
+        -- . . .    -- apply the stimulus
+      end loop stimulus_loop;
+      file_close(stimuli);
+    end loop file_loop;
+    wait;
+  end process stimulus_generator;
+
+  -- end code from book
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd
new file mode 100644
index 0000000..138ece8
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/stimulus_interpreter-1.vhd
@@ -0,0 +1,150 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity stimulus_interpreter is
+end entity stimulus_interpreter;
+
+
+architecture test of stimulus_interpreter is
+
+  quantity temperature : real;
+  signal temp_sig, setting : real;
+  signal enable, heater_fail : bit;
+
+begin
+
+-- code from book
+
+stimulus_interpreter : process is
+
+  use std.textio.all;
+
+  file control : text open read_mode is "control";
+
+  variable command : line;
+  variable read_ok : boolean;
+  variable next_time : time;
+  variable whitespace : character;
+  variable signal_id : string(1 to 4);
+  variable temp_value, set_value : real;
+  variable on_value, fail_value : bit;
+
+begin
+
+  command_loop : while not endfile(control) loop
+
+    readline ( control, command );
+
+    -- read next stimulus time, and suspend until then
+    read ( command, next_time, read_ok );
+    if not read_ok then
+      report "error reading time from line: " & command.all
+        severity warning;
+      next command_loop;
+    end if;
+    wait for next_time - now;
+
+    -- skip whitespace
+    while command'length > 0
+      and ( command(command'left) = ' '    -- ordinary space
+            or command(command'left) = ' '  -- non-breaking space
+            or command(command'left) = HT ) loop
+      read ( command, whitespace );
+    end loop;
+
+    -- read signal identifier string
+    read ( command, signal_id, read_ok );
+    if not read_ok then
+      report "error reading signal id from line: " & command.all
+        severity warning;
+      next command_loop;
+    end if;
+    -- dispatch based on signal id
+    case signal_id is
+
+      when "temp" =>
+        read ( command, temp_value, read_ok );
+        if not read_ok then
+          report "error reading temperature value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        temp_sig <= temp_value;
+
+      when "set " =>
+        -- . . .    -- similar to "temp"
+
+        -- not in book
+        read ( command, set_value, read_ok );
+        if not read_ok then
+          report "error reading setting value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        setting <= set_value;
+        -- end not in book
+
+      when "on  " =>
+        read ( command, on_value, read_ok );
+        if not read_ok then
+          report "error reading on value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        enable <= on_value;
+
+      when "fail" =>
+        -- . . .    -- similar to "on  "
+
+        -- not in book
+        read ( command, fail_value, read_ok );
+        if not read_ok then
+          report "error reading fail value from line: "
+                 & command.all
+            severity warning;
+          next command_loop;
+        end if;
+        heater_fail <= fail_value;
+        -- end not in book
+
+      when others =>
+        report "invalid signal id in line: " & signal_id
+          severity warning;
+        next command_loop;
+
+    end case;
+
+  end loop command_loop;
+
+  wait;
+
+end process stimulus_interpreter;
+
+-- end code from book
+
+-- code from book (in text)
+
+temperature == temp_sig'ramp;
+
+-- end code from book (in text)
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd
new file mode 100644
index 0000000..7aece5f
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_ROM.vhd
@@ -0,0 +1,78 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity tb_ROM_write_data is
+end entity tb_ROM_write_data;
+
+
+architecture writer of tb_ROM_write_data is
+begin
+
+  process is
+
+    subtype word is std_logic_vector(0 to 7);
+    type load_file_type is file of word;
+    file load_file : load_file_type open write_mode is "tb_ROM.dat";
+
+  begin
+    write(load_file, word'(X"00"));
+    write(load_file, word'(X"01"));
+    write(load_file, word'(X"02"));
+    write(load_file, word'(X"03"));
+    write(load_file, word'(X"04"));
+    write(load_file, word'(X"05"));
+    write(load_file, word'(X"06"));
+    write(load_file, word'(X"07"));
+    write(load_file, word'(X"08"));
+    write(load_file, word'(X"09"));
+    write(load_file, word'(X"0A"));
+    write(load_file, word'(X"0B"));
+    write(load_file, word'(X"0C"));
+    write(load_file, word'(X"0D"));
+    write(load_file, word'(X"0E"));
+    write(load_file, word'(X"0F"));
+
+    wait;
+  end process;
+
+end architecture writer;
+
+
+
+library ieee;  use ieee.std_logic_1164.all;
+
+entity tb_ROM is
+end entity tb_ROM;
+
+
+architecture test of tb_ROM is
+
+  signal sel : std_logic;
+  signal address : std_logic_vector(3 downto 0);
+  signal data : std_logic_vector(0 to 7);
+
+begin
+
+  dut : entity work.ROM(behavioral)
+    generic map ( load_file_name => "tb_ROM.dat" )
+    port map ( sel, address, data );
+
+end architecture test;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd
new file mode 100644
index 0000000..0759010
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/tb_cache.vhd
@@ -0,0 +1,86 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity tb_cache is
+end entity tb_cache;
+
+
+
+architecture test of tb_cache is
+
+  signal halt : bit := '0';
+
+begin
+
+  dut : entity work.cache(instrumented)
+    generic map ( cache_size => 128*1024, block_size => 16,
+                  associativity => 2, benchmark_name => "dhrystone " )
+    port map ( halt => halt );
+
+  halt <= '1' after 10 ns;
+
+end architecture test;
+
+
+
+entity tb_cache_read_data is
+end entity tb_cache_read_data;
+
+
+architecture reader of tb_cache_read_data is
+begin
+
+  process is
+
+    type measurement_record is
+      record
+        cache_size, block_size, associativity : positive;
+        benchmark_name : string(1 to 10);
+        miss_rate : real;
+        ave_access_time : delay_length;
+      end record;
+    type measurement_file is file of measurement_record;
+    file measurements : measurement_file open read_mode is "cache-measurements";
+    variable measurement : measurement_record;
+
+    use std.textio.all;
+    variable L : line;
+
+  begin
+    while not endfile(measurements) loop
+      read(measurements, measurement);
+      write(L, measurement.cache_size);
+      write(L, ' ');
+      write(L, measurement.block_size);
+      write(L, ' ');
+      write(L, measurement.associativity);
+      write(L, ' ');
+      write(L, measurement.benchmark_name);
+      write(L, ' ');
+      write(L, measurement.miss_rate);
+      write(L, ' ');
+      write(L, measurement.ave_access_time);
+      writeline(output, L);
+
+    end loop;
+
+    wait;
+  end process;
+
+end architecture reader;
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
new file mode 100644
index 0000000..7b5cffe
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/files-and-IO/textio.vhd
@@ -0,0 +1,91 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+package textio is
+
+  type line is access string;
+
+  type text is file of string;
+
+  type side is (right, left);
+
+  subtype width is natural;
+
+  file input : text open read_mode is "std_input";
+  file output : text open write_mode is "std_output";
+
+  -- use this declaration for VHDL-2001
+  procedure readline(file f: text; l: inout line);
+
+  -- use this declaration for VHDL-AMS
+  procedure readline(file f: text; l: out line);
+
+  procedure read ( L : inout line;  value: out bit;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit );
+
+  procedure read ( L : inout line;  value: out bit_vector;  good : out boolean );
+  procedure read ( L : inout line;  value: out bit_vector );
+
+  procedure read ( L : inout line;  value: out boolean;  good : out boolean );
+  procedure read ( L : inout line;  value: out boolean );
+
+  procedure read ( L : inout line;  value: out character;  good : out boolean );
+  procedure read ( L : inout line;  value: out character );
+
+  procedure read ( L : inout line;  value: out integer;  good : out boolean );
+  procedure read ( L : inout line;  value: out integer );
+
+  procedure read ( L : inout line;  value: out real;  good : out boolean );
+  procedure read ( L : inout line;  value: out real );
+
+  procedure read ( L : inout line;  value: out string;  good : out boolean );
+  procedure read ( L : inout line;  value: out string );
+
+  procedure read ( L : inout line;  value: out time;  good : out boolean );
+  procedure read ( L : inout line;  value: out time );
+
+  procedure writeline ( file f : text;  L : inout line );
+
+  procedure write ( L : inout line;  value : in bit;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in bit_vector;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in boolean;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in character;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in integer;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in real;
+                    justified: in side := right;  field: in width := 0;
+                    digits: in natural := 0 );
+
+  procedure write ( L : inout line;  value : in string;
+                    justified: in side := right;  field: in width := 0 );
+
+  procedure write ( L : inout line;  value : in time;
+                    justified: in side := right;  field: in width := 0;
+                    unit: in time := ns );
+
+end package textio;