Import vests testsuite

1 files changed, 41 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd
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+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/reg4.vhd
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+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+entity reg4 is
+  port ( clk, clr, d0, d1, d2, d3 : in bit;
+         q0, q1, q2, q3 : out bit );
+end entity reg4;
+
+----------------------------------------------
+
+architecture struct of reg4 is
+begin
+
+  bit0 : entity work.edge_triggered_Dff(behavioral)
+    port map (d0, clk, clr, q0);
+  bit1 : entity work.edge_triggered_Dff(behavioral)
+    port map (d1, clk, clr, q1);
+  bit2 : entity work.edge_triggered_Dff(behavioral)
+    port map (d2, clk, clr, q2);
+  bit3 : entity work.edge_triggered_Dff(behavioral)
+    port map (d3, clk, clr, q3);
+
+end architecture struct;
+
+