Import vests testsuite

1 files changed, 34 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd
new file mode 100644
index 0000000..d7b8ac4
--- /dev/null
+++ b/testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/controller_with_timing-1.vhd
@@ -0,0 +1,34 @@
+
+-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- VESTs is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU General Public License as published by the
+-- Free Software Foundation; either version 2 of the License, or (at
+-- your option) any later version. 
+
+-- VESTs is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for more details. 
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+configuration controller_with_timing of control_section is
+
+  for structural
+
+    for flag_reg : reg
+      generic map ( t_setup => 200 ps, t_hold => 150 ps,
+                    t_pd => 150 ps, width => width )
+      port map ( reset_n => '1' );
+    end for;
+
+    -- . . .
+
+  end for;
+
+end configuration controller_with_timing;