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authorTristan Gingold2013-12-20 04:48:54 +0100
committerTristan Gingold2013-12-20 04:48:54 +0100
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Import vests testsuite
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+
+-- Copyright (C) 2001-2002 The University of Cincinnati.
+-- All rights reserved.
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: test174.ams,v 1.1 2002-03-27 22:11:20 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+----------------------------------------------------------------------
+-- SIERRA REGRESSION TESTING MODEL
+-- Develooped at:
+-- Distriburted Processing Laboratory
+-- University of Cincinnati
+----------------------------------------------------------------------
+-- File : test174.ams
+-- Author(s) : Geeta Balarkishnan(gbalakri@ececs.uc.edu)
+-- Created : Sept 2001
+----------------------------------------------------------------------
+-- Description :
+----------------------------------------------------------------------
+-- A simple resistor model...
+-- the test is done for checking the correct implementation
+--of the simultaneous case statement.it checks
+--nature declaration, terminal and quantity declarations
+
+PACKAGE electricalSystem IS
+ NATURE electrical IS real ACROSS real THROUGH Ground reference ;
+ FUNCTION SIN (X : real ) RETURN real;
+ FUNCTION EXP (X : real ) RETURN real;
+END PACKAGE electricalSystem;
+
+USE work.electricalSystem.all;
+
+ENTITY simcase IS
+END simcase;
+
+ARCHITECTURE asimcase OF simcase IS
+
+ terminal T1, T2 : electrical;
+
+ quantity v1 across i1 through T1 ;
+ quantity v2 across i2 through T1 to T2;
+ quantity v3 across i3 through T2 ;
+
+BEGIN
+
+ eqn1 : v1 == 1.0;
+
+c1: case (v1*2.0) use
+
+ when (2.0) =>
+ v2 == i2 * 100.0;
+ v3 == i3 * 100.0;
+ when (6.0) =>
+ v2 == i2 * 200.0;
+ v3 == i3 * 200.0;
+ when (10.0) =>
+ v2 == i2 * 300.0;
+ v3 == i3 * 300.0;
+ when others =>
+ v2 == i2 * 400.0;
+ v3 == i3 * 400.0;
+ end case c1;
+
+END asimcase ;