Import vests testsuite

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+
+-- Copyright (C) 2000-2002 The University of Cincinnati.  
+-- All rights reserved. 
+
+-- This file is part of VESTs (Vhdl tESTs).
+
+-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE
+-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
+-- OR NON-INFRINGEMENT.  UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY
+-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR
+-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
+
+-- By using or copying this Software, Licensee agrees to abide by the
+-- intellectual property laws, and all other applicable laws of the U.S.,
+-- and the terms of this license.
+
+-- You may modify, distribute, and use the software contained in this
+-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2,
+-- June 1991. A copy of this license agreement can be found in the file
+-- "COPYING", distributed with this archive.
+
+-- You should have received a copy of the GNU General Public License
+-- along with VESTs; if not, write to the Free Software Foundation,
+-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+
+-- ---------------------------------------------------------------------
+--
+-- $Id: mixed_2.ams,v 1.1 2002-03-27 22:11:18 paw Exp $
+-- $Revision: 1.1 $
+--
+-- ---------------------------------------------------------------------
+
+PACKAGE electricalSystem IS
+    NATURE electrical IS real ACROSS real THROUGH Ground reference;
+    FUNCTION SIN(X : real) RETURN real;
+    FUNCTION EXP(X : real) RETURN real;
+    FUNCTION SQRT(X : real) RETURN real;
+    FUNCTION POW(X,Y : real) RETURN real;
+END PACKAGE electricalSystem;
+
+use work.electricalsystem.all;
+USE std.textio.ALL;
+--entity declaration
+
+ENTITY RLC IS
+
+END RLC;
+
+--architecture declaration
+
+ARCHITECTURE behavior  OF RLC IS
+
+   terminal n1, n2, n3 : electrical;
+
+   quantity vr1 across ir1 through n1 to n2;
+   quantity vr2 across ir2 through n2 to n3;
+   quantity vr3 across ir3 through n3;
+   quantity vs across n1;
+   constant r1 : REAL := 10.0;
+   constant r2 : REAL := 20.0;
+   constant r3 : REAL := 50.0;
+   signal y,x:bit := '0';
+
+BEGIN 
+
+  process(y)
+  begin
+  y <= not(y) after 30 ns;
+  end process;
+
+  process(x)
+  begin
+  x <= not(x) after 50 ns;
+  end process;
+
+testbench:PROCESS(y,x)
+    VARIABLE outline : LINE;
+    VARIABLE Headline   : string(1 TO 52) :=
+      "time  y x";
+    VARIABLE   seperator    : string(1 TO 1) := " ";
+    VARIABLE   flag     : bit := '0';
+    FILE outfile: text OPEN WRITE_MODE IS "mixed_2.out";
+  BEGIN
+    IF (flag = '0') THEN
+      flag := '1';
+      WRITE(outline,Headline);
+      WRITELINE(outfile,outline);
+    ELSE
+      WRITE(outline, now);
+      WRITE(outline,seperator);  
+      WRITE(outline, y);
+      WRITE(outline, seperator);
+      WRITE(outline, x);
+      WRITE(outline, seperator);
+      WRITELINE(outfile,outline);
+    END IF;
+  END PROCESS;
+                
+res1 : vr1 == ir1 * r1;
+res2 : vr2 == ir2 * r2;
+res3 : vr3 == ir3 * r3;
+vsrc : vs  == 5.0 * sin(2.0 * 3.1415 * 10.0 --sine source
+                               * real(time'pos(now)) * 1.0e-9);
+
+END architecture behavior;