Import vests testsuite

6 files changed, 229 insertions, 0 deletions

diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/.cvsignore b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/.cvsignore
new file mode 100644
index 0000000..681ae24
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/.cvsignore
@@ -0,0 +1 @@
+work._savant_lib
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl
new file mode 100644
index 0000000..d162a11
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl
@@ -0,0 +1,41 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two
+    port (
+      int_out : out integer);
+  end component;
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two
+    port map (
+      int_out => int_signal );
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl
new file mode 100644
index 0000000..c43c3e2
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-config-spec.vhdl
@@ -0,0 +1,46 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two
+    port (
+      int_out : out integer);
+  end component;
+
+  for ft0 : forty_two
+    use entity work.forty_two(only)
+      port map ( int_out => int_out );
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two
+    port map (
+      int_out => int_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl
new file mode 100644
index 0000000..60695f9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-with-port-map.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    int_out : out integer);
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    int_out <= 42;
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_int_out : out integer);
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        int_out => c_int_out);
+  
+  signal int_signal : integer;
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_int_out => int_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert int_signal = 42 report "TEST FAILED" severity ERROR;
+    assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/simple-array-example.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/simple-array-example.vhdl
new file mode 100644
index 0000000..aa08f64
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/simple-array-example.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    bv4_out : out bit_vector( 3 downto 0 ));
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    bv4_out <= "0110";
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_bv4_out : out bit_vector( 3 downto 0 ));
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        bv4_out => c_bv4_out );
+  
+  signal bv4_signal : bit_vector( 3 downto 0 );
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_bv4_out => bv4_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert bv4_signal = "0110" report "TEST FAILED" severity ERROR;
+    assert not(bv4_signal = "0110") report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl
new file mode 100644
index 0000000..1a021e3
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/unconstrained-array-example.vhdl
@@ -0,0 +1,47 @@
+entity forty_two is
+  port (
+    bv_out : out bit_vector );
+end forty_two;
+
+architecture only of forty_two is
+begin  -- only
+  process
+  begin  -- process
+    bv_out <= "0110";
+    wait;
+  end process;
+end only;
+
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+
+  component forty_two_component
+    port (
+      c_bv_out : out bit_vector );
+  end component;
+
+  for ft0 : forty_two_component
+    use entity work.forty_two(only)
+      port map (
+        bv_out => c_bv_out );
+  
+  signal bv_signal : bit_vector( 3 downto 0 );
+
+begin  -- only
+
+  ft0 : component forty_two_component
+    port map (
+      c_bv_out => bv_signal );
+
+
+  test: process
+  begin  -- process test
+    wait for 1 ms;
+    assert bv_signal = "0110" report "TEST FAILED" severity ERROR;
+    assert not(bv_signal = "0110") report "TEST PASSED" severity NOTE;
+    wait;
+  end process test;
+  
+end only;