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| author | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
|---|---|---|
| committer | Tristan Gingold | 2013-12-20 04:48:54 +0100 |
| commit | 6c3f709174e8e4d5411f851cedb7d84c38d3b04a (patch) | |
| tree | bd12c79c71a2ee65899a9ade9919ec2045addef8 /testsuite/vests/vhdl-93/billowitch/disputed | |
| parent | bd4aff0f670351c0652cf24e9b04361dc0e3a01c (diff) | |
| download | ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.gz ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.tar.bz2 ghdl-6c3f709174e8e4d5411f851cedb7d84c38d3b04a.zip | |
Import vests testsuite
Diffstat (limited to 'testsuite/vests/vhdl-93/billowitch/disputed')
40 files changed, 3333 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/README b/testsuite/vests/vhdl-93/billowitch/disputed/README new file mode 100644 index 0000000..52e423b --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/README @@ -0,0 +1,61 @@ +############################################################################ +################ Error cases in Billowitch ################################ +############################################################################ + +[1]tc1158.vhd : synopsys treats differently the BASE attribute +[2]tc2284.vhd : synopsys problem with multiplication and division of physical + types and real and integer +[3]tc2568.vhd : synopsys problem with universal real types, addition and + equality +[4]tc814.vhd : wrong test case, should be PASSED TEST and not FAILED TEST +[5]tc1120.vhd : type of the constrained range of the unconstrained array is + not given +[6]tc1148.vhd : type mismatch error +[7]tc1150.vhd : same as above. +[8]tc1779.vhd : Guess it is a typo, defining a architecture of an entity + which is defined later. +[9]tc232.vhdl : synopsys reports the following error : "Numeric type + definition range must be locally static". +[10]tc233.vhd : same as above +[11]tc237.vhd : same as above +[12]tc238.vhd : same as above +[13]tc3090.vhd : Synopsys reports that the attribute specification is wrong. + Name must denote entity of specified class in this + declarative region. +[14]tc3124.vhd : Synopsys reports "component local ----- must be + associated as an actual with at least one entity formal". +[15]tc3129.vhd : ,, +[16]tc3130.vhd : ,, +[17]tc3131.vhd : ,, +[18]tc3132.vhd : ,, +[19]tc3133.vhd : ,, +[20]tc3134.vhd : ,, +[21]tc3135.vhd : ,, +[22]tc3136.vhd : ,, +[23]tc851.vhd : Synopsys reports the following error : + for G(three downto zero ) + ^ + Slice discrete range direction is opposite that to prefix. +[24]tc865.vhd : ,, +[25]tc882.vhd : word work missing in the entity used in the configuration + declaration +[27]tc996.vhd : non-existing architecture name +[28]tc1021.vhd : has two blocks. when simulating in SYnopsys, it goes on + for ever. There is no termination condition. +[29]tc1737.vhd : works correctly in synopsys. But runs forever. +[30]tc1738.vhd : ,, +[31]tc3065.vhd : ,, +[32]tc1675.vhd : synopsys hangs, but gives the "passed test" message +[33]tc1740.vhd : synopsys hangs, but gives the "passed test" message +[34]tc1749.vhd : ,, +[35]tc3018.vhd : correct, but can't be simulated because, it is just a package +[36]tc737.vhd : Top level entity has a generic (GC3) with no default value. +[37]tc758.vhd : Synopsys gives this error message:Top level entity has a port + (VGEN18) which is either unconstrained/is of mode IN and has + no default value. +[38]tc816.vhd : Synopsys does not give "PASSED TEST", but if the order of + architecture is changed, then it is works. +[39]tc833.vhd : does not print "FAILED TEST" or "PASSED TEST",because there is + only "FAILED TEST" in the file and that too is commented + out. Dont know why !! . + diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd new file mode 100644 index 0000000..07aa847 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1021.vhd @@ -0,0 +1,61 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1021.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c06s03b00x00p10n01i01021ent IS +END c06s03b00x00p10n01i01021ent; + +ARCHITECTURE c06s03b00x00p10n01i01021arch OF c06s03b00x00p10n01i01021ent IS +BEGIN + B1:Block + signal s1 : BIT; + begin + TESTING: PROCESS + BEGIN + wait for 1 ns; + END PROCESS TESTING; + + B2:Block + signal s2 : BIT; + begin + TEST : PROCESS + BEGIN + s2 <= B1.s1; + wait for 2 ns; + assert NOT(s2='0') + report "***PASSED TEST: c06s03b00x00p10n01i01021" + severity NOTE; + assert (s2='0') + report "***FAILED TEST: c06s03b00x00p10n01i01021 - Entity declaration does not occur in construct specifed by the prefix." + severity ERROR; + END PROCESS TEST; + end block B2; + end block B1; + +END c06s03b00x00p10n01i01021arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd new file mode 100644 index 0000000..cfe0f35 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1120.vhd @@ -0,0 +1,85 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1120.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c06s05b00x00p03n01i01120ent IS + type idx is range 1 to 10; + type aray1 is array (idx) of bit; + type aray2 is array (idx range <>) of aray1; +END c06s05b00x00p03n01i01120ent; + +ARCHITECTURE c06s05b00x00p03n01i01120arch OF c06s05b00x00p03n01i01120ent IS + +BEGIN + TESTING: PROCESS + variable v1, v2 : aray1; + variable v3 : aray2(1 to 2); + variable v4 : aray2(1 to 3); + BEGIN + -- + -- Try slices consisting of slice names + -- + v1 := "1111111111"; + v1 := v3(1)(idx); -- slice is a whole array + assert v2 = v1 + report "Slice of a slice name as a value failed." + severity note ; + + v1 := "1111111111"; + v4(2)(idx) := v1; -- slice is a whole array + assert v4(2) = v1 + report "Slice of a slice name as a target failed." + severity note ; + + v2(1) := v3(1)(1 to 1)(1 to 1)(1); -- a one element slice + assert v3(1)(1) = v2(1) + report "One element slice of a slice name as a value failed." + severity note ; + + v3(1)(1 to 1)(1 to 1)(1) := v1(1); -- a one element slice + assert v3(1)(1) = v1(1) + report "One element slice of a slice name as a target failed." + severity note ; + + assert NOT( v1 = "1111111111" and + v4(2) = "1111111111" and + v2(1) = '0' and + v3(1)(1) = '1') + report "***PASSED TEST: c06s05b00x00p03n01i01120" + severity NOTE; + assert ( v1 = "1111111111" and + v4(2) = "1111111111" and + v2(1) = '0' and + v3(1)(1) = '1') + report "***FAILED TEST: c06s05b00x00p03n01i01120 - The prefix of a slice may be a slice name." + severity ERROR; + wait; + END PROCESS TESTING; + +END c06s05b00x00p03n01i01120arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd new file mode 100644 index 0000000..3aa1d99 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1148.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1148.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c06s05b00x00p07n01i01148ent IS +END c06s05b00x00p07n01i01148ent; + +ARCHITECTURE c06s05b00x00p07n01i01148arch OF c06s05b00x00p07n01i01148ent IS + type A is array (10 downto 1) of integer; +BEGIN + TESTING: PROCESS + variable var : A := (66,66,others=>66); + BEGIN + wait for 5 ns; + assert NOT( var(1 downto 1) = 66 ) + report "***PASSED TEST: c06s05b00x00p07n01i01148" + severity NOTE; + assert ( var(1 downto 1) = 66 ) + report "***FAILED TEST: c06s05b00x00p07n01i01148 - A(N downto N) should be a slice that contains one element." + severity ERROR; + wait; + END PROCESS TESTING; + +END c06s05b00x00p07n01i01148arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1150.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1150.vhd new file mode 100644 index 0000000..4ccd13c --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1150.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1150.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c06s05b00x00p07n01i01150ent IS +END c06s05b00x00p07n01i01150ent; + +ARCHITECTURE c06s05b00x00p07n01i01150arch OF c06s05b00x00p07n01i01150ent IS + type A is array (1 to 10) of integer; +BEGIN + TESTING: PROCESS + variable var : A := (6,6,others=>88); + BEGIN + wait for 5 ns; + assert NOT( var(1 to 1) = 6 ) + report "***PASSED TEST: c06s05b00x00p07n01i01150" + severity NOTE; + assert ( var(1 to 1) = 6 ) + report "***FAILED TEST: c06s05b00x00p07n01i01150 - A(N to N) should be a slice that contains one element." + severity ERROR; + wait; + END PROCESS TESTING; + +END c06s05b00x00p07n01i01150arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd new file mode 100644 index 0000000..85702fb --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1158.vhd @@ -0,0 +1,64 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1158.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c06s06b00x00p02n01i01158pkg is + type I1 is range 1 to 5; + subtype I11 is I1 range 2 to 4; + type A1 is array (I1 range 2 to 4) of BOOLEAN; +end c06s06b00x00p02n01i01158pkg; + +use work.c06s06b00x00p02n01i01158pkg.all; +ENTITY c06s06b00x00p02n01i01158ent IS + generic (V_all : A1 := (true,false,true)); + port (PT: BOOLEAN); +END c06s06b00x00p02n01i01158ent; + +ARCHITECTURE c06s06b00x00p02n01i01158arch OF c06s06b00x00p02n01i01158ent IS + +BEGIN + TESTING: PROCESS + variable V : boolean; + attribute AT1 : A1; + attribute AT1 of V : variable is V_all; + variable k : integer := 0; + BEGIN + if I11'BASE'Left = 1 then + k := 5; + end if; + assert NOT( k=5 ) + report "***PASSED TEST: c06s06b00x00p02n01i01158" + severity NOTE; + assert ( k=5 ) + report "***FAILED TEST: c06s06b00x00p02n01i01158 - The prefix of an attribute name may be a selected name." + severity ERROR; + wait; + END PROCESS TESTING; + +END c06s06b00x00p02n01i01158arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd new file mode 100644 index 0000000..e71aa98 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1675.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1675.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c09s01b00x00p06n01i01675ent IS +END c09s01b00x00p06n01i01675ent; + +ARCHITECTURE c09s01b00x00p06n01i01675arch OF c09s01b00x00p06n01i01675ent IS + signal garde : boolean := true; +BEGIN + lab: block ( garde ) + begin + garde <= not GUARD after 20 ns; + assert ( GUARD = garde ) + report "***FAILED TEST: c09s01b00x00p06n01i01675 - Implicit signal GUARD changed state and does not match explicit signal garde (FAIL)" + severity ERROR; + end block lab; + + TESTING: PROCESS + BEGIN + assert FALSE + report "***PASSED TEST: c09s01b00x00p06n01i01675 - This test needed manual check, no failure test assertion report" + severity NOTE; + wait; + END PROCESS TESTING; + +END c09s01b00x00p06n01i01675arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1737.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1737.vhd new file mode 100644 index 0000000..90ec747 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1737.vhd @@ -0,0 +1,55 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1737.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c09s04b00x00p09n01i01737ent IS +END c09s04b00x00p09n01i01737ent; + +ARCHITECTURE c09s04b00x00p09n01i01737arch OF c09s04b00x00p09n01i01737ent IS + signal s1 : bit; + signal s2 : bit; +BEGIN + + s1 <= not s1 after 70 ns; + s2 <= not s2 after 30 ns; + + block_label1 : BLOCK (s1 = '1') + begin + assert (s2 = s2'last_value) + report "PASSED TEST" + severity NOTE; + TESTING: PROCESS(s2) + BEGIN + assert FALSE + report "***PASSED TEST: c09s04b00x00p09n01i01737 - This test needs manual check, depend on the simulation time, the assertion 'PASSED TEST' should fire every time s2 is changed regardless of the value of the signal GUARD." + severity NOTE; + END PROCESS TESTING; + end block block_label1; + +END c09s04b00x00p09n01i01737arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd new file mode 100644 index 0000000..b9bcf2c --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1738.vhd @@ -0,0 +1,56 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1738.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c09s04b00x00p09n01i01738ent IS +END c09s04b00x00p09n01i01738ent; + +ARCHITECTURE c09s04b00x00p09n01i01738arch OF c09s04b00x00p09n01i01738ent IS + signal s1 : bit; +BEGIN + + s1 <= not s1 after 70 ns; + + block_label1 : BLOCK (s1 = '1') + begin + assert not GUARD + report "PASSED TEST" + severity NOTE; + end block block_label1; + + TESTING: PROCESS(s1) + BEGIN + if (now = 70 ns) then + assert FALSE + report "***PASSED TEST: c09s04b00x00p09n01i01738 - This test needs manual check, 'PASSED TEST' assertion should fire at 70 ns, 210 ns, 350 ns ...( the cycle is 140 ns)." + severity NOTE; + end if; + END PROCESS TESTING; + +END c09s04b00x00p09n01i01738arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1740.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1740.vhd new file mode 100644 index 0000000..fdf61a5 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1740.vhd @@ -0,0 +1,47 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1740.vhd,v 1.2 2001-10-26 16:30:03 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c09s05b00x00p02n01i01740ent IS + port (clk : inout bit); +END c09s05b00x00p02n01i01740ent; + +ARCHITECTURE c09s05b00x00p02n01i01740arch OF c09s05b00x00p02n01i01740ent IS + constant period : Time := 50 ns; +BEGIN + osc: clk <= not clk after period/2; -- No_failure_here + TESTING: PROCESS + BEGIN + assert FALSE + report "***PASSED TEST: c09s05b00x00p02n01i01740" + severity NOTE; + wait; + END PROCESS TESTING; + +END c09s05b00x00p02n01i01740arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1749.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1749.vhd new file mode 100644 index 0000000..43082e3 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1749.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1749.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c09s05b00x00p16n01i01749ent IS +END c09s05b00x00p16n01i01749ent; + +ARCHITECTURE c09s05b00x00p16n01i01749arch OF c09s05b00x00p16n01i01749ent IS + signal a : bit; + signal b : bit; + signal grd : boolean; +BEGIN + grd <= not grd after 75 ns; + + block_label : BLOCK (grd) + begin + b <= guarded '1' after 1 ns; + end block block_label; + + BG: block (grd) + begin + TESTING: PROCESS + BEGIN + if GUARD then + a <= '1' after 1 ns; + end if; + wait on GUARD, a; + END PROCESS TESTING; + end block BG; + + process(a,b) + begin + if (now > 1 ns) then + assert NOT( a=b ) + report "***PASSED TEST: c09s05b00x00p16n01i01749" + severity NOTE; + assert ( a=b ) + report "***FAILED TEST: c09s05b00x00p16n01i01749 - Concurrent signal assignment test failed." + severity ERROR; + end if; + end process; + +END c09s05b00x00p16n01i01749arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc1779.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc1779.vhd new file mode 100644 index 0000000..7e93424 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc1779.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc1779.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c09s06b00x00p02n01i01779ent_a IS + port (signal input_1 : in bit; + signal input_2 : in bit; + signal output : out bit); +END c09s06b00x00p02n01i01779ent_a; + +ARCHITECTURE c09s06b00x00p02n01i01779arch_a OF c09s06b00x00p02n01i01779ent IS + +BEGIN + +END c09s06b00x00p02n01i01779arch_a; + +ENTITY c09s06b00x00p02n01i01779ent IS +END c09s06b00x00p02n01i01779ent; + +ARCHITECTURE c09s06b00x00p02n01i01779arch OF c09s06b00x00p02n01i01779ent IS + + component input2 + port (signal input_1 : in bit; + signal input_2 : in bit; + signal output : out bit); + end component; + for C : input2 use entity work.c09s06b00x00p02n01i01779ent_a(c09s06b00x00p02n01i01779arch_a); + + signal A1, A2, A3 : bit; + +BEGIN + + C : input2 port map (A1,A2,A3); + + TESTING: PROCESS + BEGIN + assert FALSE + report "***PASSED TEST: c09s06b00x00p02n01i01779" + severity NOTE; + wait; + END PROCESS TESTING; + +END c09s06b00x00p02n01i01779arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd new file mode 100644 index 0000000..fd38584 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc2284.vhd @@ -0,0 +1,53 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc2284.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c07s02b06x00p14n01i02284ent IS +END c07s02b06x00p14n01i02284ent; + +ARCHITECTURE c07s02b06x00p14n01i02284arch OF c07s02b06x00p14n01i02284ent IS + signal SS : TIME; +BEGIN + TESTING: PROCESS + variable A : TIME := 199 ns; + variable R : REAL := 7.9999; + variable S : INTEGER := 199; + BEGIN + SS <= A * R / S; + wait for 10 ns; + assert NOT(SS = 7.9999 ns) + report "***PASSED TEST: c07s02b06x00p14n01i02284" + severity NOTE; + assert (SS = 7.9999 ns) + report "***FAILED TEST: c07s02b06x00p14n01i02284 - Incompatible operands: May not be multiplied or divided." + severity ERROR; + wait; + END PROCESS TESTING; + +END c07s02b06x00p14n01i02284arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd new file mode 100644 index 0000000..5ff3046 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc232.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc232.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c03s01b02x00p02n01i00232ent IS +END c03s01b02x00p02n01i00232ent; + +ARCHITECTURE c03s01b02x00p02n01i00232arch OF c03s01b02x00p02n01i00232ent IS + type a is range (1+1) to (1 ms/1 ns); +BEGIN + TESTING: PROCESS + variable k : a := 3; + BEGIN + k := 5; + assert NOT(k=5) + report "***PASSED TEST: c03s01b02x00p02n01i00232" + severity NOTE; + assert (k=5) + report "***FAILED TEST: c03s01b02x00p02n01i00232 - The right bound in the range constraint is not a locally static expression of type integer." + severity ERROR; + wait; + END PROCESS TESTING; + +END c03s01b02x00p02n01i00232arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd new file mode 100644 index 0000000..fc31709 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc233.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c03s01b02x00p02n01i00233ent IS +END c03s01b02x00p02n01i00233ent; + +ARCHITECTURE c03s01b02x00p02n01i00233arch OF c03s01b02x00p02n01i00233ent IS + type a is range (1 ns/1 fs) downto (1 fs/1 fs); +BEGIN + TESTING: PROCESS + variable k : a := 3; + BEGIN + k := 5; + assert NOT(k=5) + report "***PASSED TEST: c03s01b02x00p02n01i00233" + severity NOTE; + assert (k=5) + report "***FAILED TEST: c03s01b02x00p02n01i00233 - The right bound in the range constraint is not a locally static expression of type integer." + severity ERROR; + wait; + END PROCESS TESTING; + +END c03s01b02x00p02n01i00233arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd new file mode 100644 index 0000000..4dd5f67 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc237.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc237.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c03s01b02x00p04n01i00237ent IS +END c03s01b02x00p04n01i00237ent; + +ARCHITECTURE c03s01b02x00p04n01i00237arch OF c03s01b02x00p04n01i00237ent IS + type t3 is range (1+1) to (ms/ns); +BEGIN + TESTING: PROCESS + variable k : integer := 6; + BEGIN + k := 5; + assert NOT(k=5) + report "***PASSED TEST: c03s01b02x00p04n01i00237" + severity NOTE; + assert (k=5) + report "***FAILED TEST: c03s01b02x00p04n01i00237 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]" + severity ERROR; + wait; + END PROCESS TESTING; + +END c03s01b02x00p04n01i00237arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd new file mode 100644 index 0000000..0c05ff7 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc238.vhd @@ -0,0 +1,50 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc238.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c03s01b02x00p04n01i00238ent IS +END c03s01b02x00p04n01i00238ent; + +ARCHITECTURE c03s01b02x00p04n01i00238arch OF c03s01b02x00p04n01i00238ent IS + type t3 is range (ns/fs) downto (fs/fs); +BEGIN + TESTING: PROCESS + variable k : integer := 6; + BEGIN + k := 5; + assert NOT(k=5) + report "***PASSED TEST: c03s01b02x00p04n01i00238" + severity NOTE; + assert (k=5) + report "***FAILED TEST: c03s01b02x00p04n01i00238 - Each each bound of a range constraint that is used in an integer type definition is a locally static expression [of some integer type, but the two bounds need not have the same integer type.]" + severity ERROR; + wait; + END PROCESS TESTING; + +END c03s01b02x00p04n01i00238arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd new file mode 100644 index 0000000..567544a --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc2568.vhd @@ -0,0 +1,48 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc2568.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c07s05b00x00p02n01i02568ent IS +END c07s05b00x00p02n01i02568ent; + +ARCHITECTURE c07s05b00x00p02n01i02568arch OF c07s05b00x00p02n01i02568ent IS + +BEGIN + TESTING: PROCESS + BEGIN + assert NOT(6.023E+24 = (2.003E+24 + 4.02E+24)) + report "***PASSED TEST: c07s05b00x00p02n01i02568" + severity NOTE; + assert (6.023E+24 = (2.003E+24 + 4.02E+24)) + report "***FAILED TEST: c07s05b00x00p02n01i02568 - The same operations are defined for the type universal_integer as for any integer type." + severity ERROR; + wait; + END PROCESS TESTING; + +END c07s05b00x00p02n01i02568arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3018.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3018.vhd new file mode 100644 index 0000000..4afca98 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3018.vhd @@ -0,0 +1,33 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3018.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c11s02b00x00p05n03i03018pkg IS + constant my_bool : boolean := false; +END c11s02b00x00p05n03i03018pkg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd new file mode 100644 index 0000000..37d3730 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3065.vhd @@ -0,0 +1,59 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c12s04b02x00p02n01i03065ent IS +END c12s04b02x00p02n01i03065ent; + +ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS + type intvector is array (natural range <>) of integer; + signal V2 : intvector(1 to 5); + signal V0 : integer := 66; +BEGIN + FG2: for i in V2'range generate + IG1: if i = V2'left generate + V2(i) <= V0 after 1 ns; + end generate; + IG2: if i /= V2'left generate + V2(i) <= V2(i-1) after 1 ns; + end generate; + -- ..., V2(2) <= V2(1), V2(1) <= V0 + end generate; + TESTING: PROCESS + BEGIN + wait for 50 ns; + assert NOT( V2 = (66,66,66,66,66) ) + report "***PASSED TEST: c12s04b02x00p02n01i03065" + severity NOTE; + assert ( V2 = (66,66,66,66,66) ) + report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed." + severity ERROR; + END PROCESS TESTING; + +END c12s04b02x00p02n01i03065arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3090.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3090.vhd new file mode 100644 index 0000000..ff4e3aa --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3090.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3090.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s01b00x00p02n01i03090ent IS +END c05s01b00x00p02n01i03090ent; + +ARCHITECTURE c05s01b00x00p02n01i03090arch OF c05s01b00x00p02n01i03090ent IS + type a is range 1 to 10; + attribute arbitrary : integer; + attribute arbitrary of a : type is 5; -- No_Failure_here +BEGIN + TESTING: PROCESS + BEGIN + wait for 5 ns; + assert NOT( a'arbitrary = 5 ) + report "***PASSED TEST: c05s01b00x00p02n01i03090" + severity NOTE; + assert ( a'arbitrary = 5 ) + report "***FAILED TEST: c05s01b00x00p02n01i03090 - Attribute specification syntax test failed." + severity ERROR; + wait; + END PROCESS TESTING; + +END c05s01b00x00p02n01i03090arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd new file mode 100644 index 0000000..d8bb477 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3124.vhd @@ -0,0 +1,186 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3124.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p01n01i03124ent_a IS + generic ( socket_g1 : Boolean; + socket_g2 : Bit; + socket_g3 : character; + socket_g4 : severity_level; + socket_g5 : integer; + socket_g6 : real; + socket_g7 : time; + socket_g8 : natural; + socket_g9 : positive + ); + port ( socket_p1 : inout Boolean; + socket_p2 : inout Bit; + socket_p3 : inout character; + socket_p4 : inout severity_level; + socket_p5 : inout integer; + socket_p6 : inout real; + socket_p7 : inout time; + socket_p8 : inout natural; + socket_p9 : inout positive + ); +END c05s02b01x02p01n01i03124ent_a; + +ARCHITECTURE c05s02b01x02p01n01i03124arch_a OF c05s02b01x02p01n01i03124ent_a IS + +BEGIN + socket_p1 <= socket_g1 after 22 ns; + socket_p2 <= socket_g2 after 22 ns; + socket_p3 <= socket_g3 after 22 ns; + socket_p4 <= socket_g4 after 22 ns; + socket_p5 <= socket_g5 after 22 ns; + socket_p6 <= socket_g6 after 22 ns; + socket_p7 <= socket_g7 after 22 ns; + socket_p8 <= socket_g8 after 22 ns; + socket_p9 <= socket_g9 after 22 ns; +END c05s02b01x02p01n01i03124arch_a; + + + +ENTITY c05s02b01x02p01n01i03124ent IS +END c05s02b01x02p01n01i03124ent; + +ARCHITECTURE c05s02b01x02p01n01i03124arch OF c05s02b01x02p01n01i03124ent IS + component ic_socket + generic ( socket_g1 : Boolean; + socket_g2 : Bit; + socket_g3 : character; + socket_g4 : severity_level; + socket_g5 : integer; + socket_g6 : real; + socket_g7 : time; + socket_g8 : natural; + socket_g9 : positive + ); + port ( socket_p1 : inout Boolean; + socket_p2 : inout Bit; + socket_p3 : inout character; + socket_p4 : inout severity_level; + socket_p5 : inout integer; + socket_p6 : inout real; + socket_p7 : inout time; + socket_p8 : inout natural; + socket_p9 : inout positive + ); + end component; + signal socket_p1 : Boolean; + signal socket_p2 : Bit; + signal socket_p3 : character; + signal socket_p4 : severity_level; + signal socket_p5 : integer; + signal socket_p6 : real; + signal socket_p7 : time; + signal socket_p8 : natural; + signal socket_p9 : positive; +BEGIN + instance : ic_socket + generic map ( true, + '1', + '$', + warning, + -100002, + -9.999, + 20 ns, + 23423, + 4564576 + ) + port map ( socket_p1, + socket_p2, + socket_p3, + socket_p4, + socket_p5, + socket_p6, + socket_p7, + socket_p8, + socket_p9 + ); + + TESTING: PROCESS + BEGIN + wait for 30 ns; + assert NOT( socket_p1 = true and + socket_p2 = '1' and + socket_p3 = '$' and + socket_p4 = warning and + socket_p5 = -100002 and + socket_p6 = -9.999 and + socket_p7 = 20 ns and + socket_p8 = 23423 and + socket_p9 = 4564576 ) + report "***PASSED TEST: c05s02b01x02p01n01i03124" + severity NOTE; + assert ( socket_p1 = true and + socket_p2 = '1' and + socket_p3 = '$' and + socket_p4 = warning and + socket_p5 = -100002 and + socket_p6 = -9.999 and + socket_p7 = 20 ns and + socket_p8 = 23423 and + socket_p9 = 4564576 ) + report "***FAILED TEST: c05s02b01x02p01n01i03124 - Positional association generic and port list test failed." + severity ERROR; + wait; + END PROCESS TESTING; + +END c05s02b01x02p01n01i03124arch; + + + + +configuration c05s02b01x02p01n01i03124cfg of c05s02b01x02p01n01i03124ent is + for c05s02b01x02p01n01i03124arch + for instance : ic_socket use entity work.c05s02b01x02p01n01i03124ent_a (c05s02b01x02p01n01i03124arch_a) + generic map ( true, + '1', + '$', + warning, + -100002, + -9.999, + 20 ns, + 23423, + 4564576 + ) + port map ( socket_p1, + socket_p2, + socket_p3, + socket_p4, + socket_p5, + socket_p6, + socket_p7, + socket_p8, + socket_p9 + ); + end for; + end for; +end c05s02b01x02p01n01i03124cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3129.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3129.vhd new file mode 100644 index 0000000..5f6fc5f --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3129.vhd @@ -0,0 +1,72 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3129.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p12n01i03129ent_a IS + generic ( g1 : boolean := false ); +END c05s02b01x02p12n01i03129ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03129arch_a OF c05s02b01x02p12n01i03129ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 report "g1=false" severity FAILURE; + assert NOT( g1 = true ) + report "***PASSED TEST: c05s02b01x02p12n01i03129" + severity NOTE; + assert ( g1 = true ) + report "***FAILED TEST: c05s02b01x02p12n01i03129 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03129arch_a; + + + + +ENTITY c05s02b01x02p12n01i03129ent IS +END c05s02b01x02p12n01i03129ent; + +ARCHITECTURE c05s02b01x02p12n01i03129arch OF c05s02b01x02p12n01i03129ent IS + component ic_socket + generic ( local_g1 : Boolean := true ); + end component; +BEGIN + instance : ic_socket; +END c05s02b01x02p12n01i03129arch; + + +configuration c05s02b01x02p12n01i03129cfg of c05s02b01x02p12n01i03129ent is + for c05s02b01x02p12n01i03129arch + for instance : ic_socket use entity work.c05s02b01x02p12n01i03129ent_a (c05s02b01x02p12n01i03129arch_a) + generic map ( true ); + end for; + end for; +end c05s02b01x02p12n01i03129cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3130.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3130.vhd new file mode 100644 index 0000000..c16a637 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3130.vhd @@ -0,0 +1,71 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3130.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p12n01i03130ent_a IS + generic ( g1 : boolean := false ); +END c05s02b01x02p12n01i03130ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03130arch_a OF c05s02b01x02p12n01i03130ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 report "g1=false" severity FAILURE; + assert NOT( g1 = true ) + report "***PASSED TEST: c05s02b01x02p12n01i03130" + severity NOTE; + assert ( g1 = true ) + report "***FAILED TEST: c05s02b01x02p12n01i03130 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03130arch_a; + + + + +ENTITY c05s02b01x02p12n01i03130ent IS +END c05s02b01x02p12n01i03130ent; + +ARCHITECTURE c05s02b01x02p12n01i03130arch OF c05s02b01x02p12n01i03130ent IS + component ic_socket + generic ( local_g1 : Boolean := true ); + end component; + for instance : ic_socket use entity work.c05s02b01x02p12n01i03130ent_a (c05s02b01x02p12n01i03130arch_a) + generic map ( true ); +BEGIN + instance : ic_socket; +END c05s02b01x02p12n01i03130arch; + + +configuration c05s02b01x02p12n01i03130cfg of c05s02b01x02p12n01i03130ent is + for c05s02b01x02p12n01i03130arch + end for; +end c05s02b01x02p12n01i03130cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd new file mode 100644 index 0000000..23d79a2 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3131.vhd @@ -0,0 +1,75 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3131.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p12n01i03131ent_a IS + generic ( g1 : boolean := false ); +END c05s02b01x02p12n01i03131ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03131arch_a OF c05s02b01x02p12n01i03131ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 report "g1=false" severity FAILURE; + assert NOT( g1 = true ) + report "***PASSED TEST: c05s02b01x02p12n01i03131" + severity NOTE; + assert ( g1 = true ) + report "***FAILED TEST: c05s02b01x02p12n01i03131 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03131arch_a; + + + + +ENTITY c05s02b01x02p12n01i03131ent IS +END c05s02b01x02p12n01i03131ent; + +ARCHITECTURE c05s02b01x02p12n01i03131arch OF c05s02b01x02p12n01i03131ent IS + +BEGIN + labeled : block + component ic_socket + generic ( local_g1 : Boolean := true ); + end component; + for instance : ic_socket use entity work .c05s02b01x02p12n01i03131ent_a (c05s02b01x02p12n01i03131arch_a) + generic map ( true ); + begin + instance : ic_socket; + end block; +END c05s02b01x02p12n01i03131arch; + + +configuration c05s02b01x02p12n01i03131cfg of c05s02b01x02p12n01i03131ent is + for c05s02b01x02p12n01i03131arch + end for; +end c05s02b01x02p12n01i03131cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3132.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3132.vhd new file mode 100644 index 0000000..d8717bd --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3132.vhd @@ -0,0 +1,76 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3132.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c05s02b01x02p12n01i03132pkg is + CONSTANT do_baby : boolean := true; +end c05s02b01x02p12n01i03132pkg; + + +ENTITY c05s02b01x02p12n01i03132ent_a IS + generic ( g1 : boolean := false ); +END c05s02b01x02p12n01i03132ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03132arch_a OF c05s02b01x02p12n01i03132ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 report "g1=false" severity FAILURE; + assert NOT( g1 = true ) + report "***PASSED TEST: c05s02b01x02p12n01i03132" + severity NOTE; + assert ( g1 = true ) + report "***FAILED TEST: c05s02b01x02p12n01i03132 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03132arch_a; + + + + +ENTITY c05s02b01x02p12n01i03132ent IS +END c05s02b01x02p12n01i03132ent; + +ARCHITECTURE c05s02b01x02p12n01i03132arch OF c05s02b01x02p12n01i03132ent IS + component ic_socket + generic ( local_g1 : Boolean := true ); + end component; + for instance : ic_socket use entity work.c05s02b01x02p12n01i03132ent_a (c05s02b01x02p12n01i03132arch_a) + generic map ( work.c05s02b01x02p12n01i03132pkg.do_baby ); +BEGIN + instance : ic_socket; +END c05s02b01x02p12n01i03132arch; + + +configuration c05s02b01x02p12n01i03132cfg of c05s02b01x02p12n01i03132ent is + for c05s02b01x02p12n01i03132arch + end for; +end c05s02b01x02p12n01i03132cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3133.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3133.vhd new file mode 100644 index 0000000..439f4c1 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3133.vhd @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3133.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c05s02b01x02p12n01i03133pkg is + CONSTANT do_baby : boolean := true; +end c05s02b01x02p12n01i03133pkg; + + +ENTITY c05s02b01x02p12n01i03133ent_a IS + generic ( g1 : boolean := false ); +END c05s02b01x02p12n01i03133ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03133arch_a OF c05s02b01x02p12n01i03133ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 report "g1=false" severity FAILURE; + assert NOT( g1 = true ) + report "***PASSED TEST: c05s02b01x02p12n01i03133" + severity NOTE; + assert ( g1 = true ) + report "***FAILED TEST: c05s02b01x02p12n01i03133 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03133arch_a; + + + + +ENTITY c05s02b01x02p12n01i03133ent IS +END c05s02b01x02p12n01i03133ent; + +ARCHITECTURE c05s02b01x02p12n01i03133arch OF c05s02b01x02p12n01i03133ent IS +BEGIN + labeled : block + component ic_socket + generic ( local_g1 : Boolean := true ); + end component; + for instance : ic_socket use entity work.c05s02b01x02p12n01i03133ent_a (c05s02b01x02p12n01i03133arch_a) + generic map ( work.c05s02b01x02p12n01i03133pkg.do_baby ); + begin + instance : ic_socket; + end block; +END c05s02b01x02p12n01i03133arch; + + +configuration c05s02b01x02p12n01i03133cfg of c05s02b01x02p12n01i03133ent is + for c05s02b01x02p12n01i03133arch + end for; +end c05s02b01x02p12n01i03133cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3134.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3134.vhd new file mode 100644 index 0000000..344d81d --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3134.vhd @@ -0,0 +1,79 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3134.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p12n01i03134ent_a IS + generic ( g1 : integer := 0 ); +END c05s02b01x02p12n01i03134ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03134arch_a OF c05s02b01x02p12n01i03134ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 /= 0 report "g1 = 0 " severity FAILURE; + assert g1 /= 1 report "g1 = 1 " severity FAILURE; + assert g1 = -1 report "g1 /= -1 " severity FAILURE; + assert NOT( g1 /= 0 and + g1 /= 1 and + g1 = -1 ) + report "***PASSED TEST: c05s02b01x02p12n01i03134" + severity NOTE; + assert ( g1 /= 0 and + g1 /= 1 and + g1 = -1 ) + report "***FAILED TEST: c05s02b01x02p12n01i03134 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03134arch_a; + + + + +ENTITY c05s02b01x02p12n01i03134ent IS + generic ( test_g : integer := -1 ); +END c05s02b01x02p12n01i03134ent; + +ARCHITECTURE c05s02b01x02p12n01i03134arch OF c05s02b01x02p12n01i03134ent IS + component ic_socket + generic ( local_g1 : integer := 1 ); + end component; +BEGIN + instance : ic_socket; +END c05s02b01x02p12n01i03134arch; + + +configuration c05s02b01x02p12n01i03134cfg of c05s02b01x02p12n01i03134ent is + for c05s02b01x02p12n01i03134arch + for instance : ic_socket use entity work.c05s02b01x02p12n01i03134ent_a (c05s02b01x02p12n01i03134arch_a) + generic map (test_g); + end for; + end for; +end c05s02b01x02p12n01i03134cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd new file mode 100644 index 0000000..8a4bb23 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3135.vhd @@ -0,0 +1,78 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3135.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p12n01i03135ent_a IS + generic ( g1 : integer := 0 ); +END c05s02b01x02p12n01i03135ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03135arch_a OF c05s02b01x02p12n01i03135ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 /= 0 report "g1 = 0 " severity FAILURE; + assert g1 /= 1 report "g1 = 1 " severity FAILURE; + assert g1 = -1 report "g1 /= -1 " severity FAILURE; + assert NOT( g1 /= 0 and + g1 /= 1 and + g1 = -1 ) + report "***PASSED TEST: c05s02b01x02p12n01i03135" + severity NOTE; + assert ( g1 /= 0 and + g1 /= 1 and + g1 = -1 ) + report "***FAILED TEST: c05s02b01x02p12n01i03135 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03135arch_a; + + + + +ENTITY c05s02b01x02p12n01i03135ent IS + generic ( test_g : integer := -1 ); +END c05s02b01x02p12n01i03135ent; + +ARCHITECTURE c05s02b01x02p12n01i03135arch OF c05s02b01x02p12n01i03135ent IS + component ic_socket + generic ( local_g1 : integer := 1 ); + end component; + for instance : ic_socket use entity work.c05s02b01x02p12n01i03135ent_a (c05s02b01x02p12n01i03135arch_a) + generic map (test_g); +BEGIN + instance : ic_socket; +END c05s02b01x02p12n01i03135arch; + + +configuration c05s02b01x02p12n01i03135cfg of c05s02b01x02p12n01i03135ent is + for c05s02b01x02p12n01i03135arch + end for; +end c05s02b01x02p12n01i03135cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc3136.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc3136.vhd new file mode 100644 index 0000000..4bd7166 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc3136.vhd @@ -0,0 +1,81 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc3136.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c05s02b01x02p12n01i03136ent_a IS + generic ( g1 : integer := 0 ); +END c05s02b01x02p12n01i03136ent_a; + +ARCHITECTURE c05s02b01x02p12n01i03136arch_a OF c05s02b01x02p12n01i03136ent_a IS + +BEGIN + TESTING: PROCESS + BEGIN + assert g1 /= 0 report "g1 = 0 " severity FAILURE; + assert g1 /= 1 report "g1 = 1 " severity FAILURE; + assert g1 = -1 report "g1 /= -1 " severity FAILURE; + assert NOT( g1 /= 0 and + g1 /= 1 and + g1 = -1 ) + report "***PASSED TEST: c05s02b01x02p12n01i03136" + severity NOTE; + assert ( g1 /= 0 and + g1 /= 1 and + g1 = -1 ) + report "***FAILED TEST: c05s02b01x02p12n01i03136 - An actual associated with a formal generic in a generic map aspect be an expression test failed." + severity ERROR; + wait; + END PROCESS TESTING; +END c05s02b01x02p12n01i03136arch_a; + + + + +ENTITY c05s02b01x02p12n01i03136ent IS + generic ( test_g : integer := -1 ); +END c05s02b01x02p12n01i03136ent; + +ARCHITECTURE c05s02b01x02p12n01i03136arch OF c05s02b01x02p12n01i03136ent IS +BEGIN + labeled : block + component ic_socket + generic ( local_g1 : integer := 1 ); + end component; + for instance : ic_socket use entity work.c05s02b01x02p12n01i03136ent_a (c05s02b01x02p12n01i03136arch_a) + generic map (test_g); + begin + instance : ic_socket; + end block; +END c05s02b01x02p12n01i03136arch; + + +configuration c05s02b01x02p12n01i03136cfg of c05s02b01x02p12n01i03136ent is + for c05s02b01x02p12n01i03136arch + end for; +end c05s02b01x02p12n01i03136cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd new file mode 100644 index 0000000..c9ce7f5 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc59.vhd @@ -0,0 +1,51 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc59.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c04s03b01x01p05n01i00059ent IS +END c04s03b01x01p05n01i00059ent; + +ARCHITECTURE c04s03b01x01p05n01i00059arch OF c04s03b01x01p05n01i00059ent IS + signal S1 : integer := 10; +BEGIN + TESTING : PROCESS + variable TimeCount : time := 0 ns; + BEGIN + S1 <= transport N1 after T1 ; -- No_failure_here + wait for T1; + assert NOT(S1'active and S1 = 20) + report "***PASSED TEST:c04s03b01x01p05n01i00059" + severity NOTE; + assert (S1'active and S1 = 20) + report "***FAILED TEST:c04s03b01x01p05n01i00059 - Generics constant test failed." + severity ERROR; + wait; + END PROCESS TESTING; + +END c04s03b01x01p05n01i00059arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd new file mode 100644 index 0000000..0f7e0b3 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc737.vhd @@ -0,0 +1,122 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc737.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +entity c01s01b01x01p04n01i00737ent_a is + generic ( + constant gc1 : in integer; + constant gc2 : in real; + constant gc3 : in boolean + ); + port ( signal cent1 : in bit; + signal cent2 : in bit + ); +end c01s01b01x01p04n01i00737ent_a; + +architecture c01s01b01x01p04n01i00737arch_a of c01s01b01x01p04n01i00737ent_a is +begin + p0: process + begin + wait for 1 ns; + if (gc1 = 5) AND (gc2 = 0.1234) AND (gc3) then + assert FALSE + report "***PASSED TEST: c01s01b01x01p04n01i00737" + severity NOTE; + else + assert FALSE + report "***FAILED TEST: c01s01b01x01p04n01i00737 - Simple generic association in component instantiation (type conversion done on actual in generic map failed)." + severity ERROR; + end if; + wait; + end process; +end c01s01b01x01p04n01i00737arch_a; + + +ENTITY c01s01b01x01p04n01i00737ent IS + generic ( constant gen_con : integer := 7 ); + port ( signal ee1 : in bit; + signal ee2 : in bit; + signal eo1 : out bit + ); +END c01s01b01x01p04n01i00737ent; + +ARCHITECTURE c01s01b01x01p04n01i00737arch OF c01s01b01x01p04n01i00737ent IS + constant c1 : integer := 33; + constant c2 : real := 1.23557; + constant c3 : boolean := FALSE; + signal s1 : integer; + signal s2 : integer; + signal s3 : integer; + + component comp1 + generic ( + constant dgc1 : integer; + constant dgc2 : real; + constant dgc3 : boolean + ); + port ( signal dcent1 : in bit; + signal dcent2 : in bit + ); + end component; + + for u1 : comp1 use + entity work.c01s01b01x01p04n01i00737ent_a(c01s01b01x01p04n01i00737_arch_a) + generic map (dgc1, dgc2, dgc3) + port map ( dcent1, dcent2 ); + + function BoolToInt(bin : boolean) return integer is + begin + if bin then + return 5; + else + return 99; + end if; + end; + + function IntegerToReal(iin : integer) return real is + begin + return 0.1234; + end; + + function BitToBool(bin : bit) return boolean is + begin + if (bin = '1') then + return TRUE; + else + return FALSE; + end if; + end; + +BEGIN + + u1 : comp1 + generic map (BoolToInt(TRUE), IntegerToReal(1234), BitToBool('1')) + port map (ee1,ee2); + +END c01s01b01x01p04n01i00737arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd new file mode 100644 index 0000000..b4e9123 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc758.vhd @@ -0,0 +1,186 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc758.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c01s01b01x01p05n02i00758pkg is + +--UNCONSTRAINED ARRAY OF TYPES FROM STANDARD PACKAGE +--Index type is natural + type boolean_vector is array (natural range <>) of boolean; + type severity_level_vector is array (natural range <>) of severity_level; + type integer_vector is array (natural range <>) of integer; + type real_vector is array (natural range <>) of real; + type time_vector is array (natural range <>) of time; + type natural_vector is array (natural range <>) of natural; + type positive_vector is array (natural range <>) of positive; + + constant C1 : boolean := true; + constant C2 : bit := '1'; + constant C3 : character := 's'; + constant C4 : severity_level:= note; + constant C5 : integer := 3; + constant C6 : real := 3.0; + constant C7 : time := 3 ns; + constant C8 : natural := 1; + constant C9 : positive := 1; + constant C10 : string := "shishir"; + constant C11 : bit_vector := B"0011"; + constant C12 : boolean_vector:= (true,false); + constant C13 : severity_level_vector := (note,error); + constant C14 : integer_vector:= (1,2,3,4); + constant C15 : real_vector := (1.0,2.0,3.0,4.0); + constant C16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns); + constant C17 : natural_vector:= (1,2,3,4); + constant C18 : positive_vector:= (1,2,3,4); + +end c01s01b01x01p05n02i00758pkg; + +use work.c01s01b01x01p05n02i00758pkg.ALL; +ENTITY c01s01b01x01p05n02i00758ent IS + generic( + zero : integer := 0; + one : integer := 1; + two : integer := 2; + three : integer := 3; + four : integer := 4; + five : integer := 5; + six : integer := 6; + seven : integer := 7; + eight : integer := 8; + nine : integer := 9; + fifteen : integer:= 15; + Cgen1 : boolean := true; + Cgen2 : bit := '1'; + Cgen3 : character := 's'; + Cgen4 : severity_level := note; + Cgen5 : integer := 3; + Cgen6 : real := 3.0; + Cgen7 : time := 3 ns; + Cgen8 : natural := 1; + Cgen9 : positive := 1; + Cgen10 : string := "shishir"; + Cgen11 : bit_vector := B"0011"; + Cgen12 : boolean_vector := (true,false); + Cgen13 : severity_level_vector := (note,error); + Cgen14 : integer_vector := (1,2,3,4); + Cgen15 : real_vector := (1.0,2.0,3.0,4.0); + Cgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns); + Cgen17 : natural_vector := (1,2,3,4); + Cgen18 : positive_vector := (1,2,3,4) ); + port( + Vgen1 : boolean := true; + Vgen2 : bit := '1'; + Vgen3 : character := 's'; + Vgen4 : severity_level:= note; + Vgen5 : integer := 3; + Vgen6 : real := 3.0; + Vgen7 : time := 3 ns; + Vgen8 : natural := 1; + Vgen9 : positive := 1; + Vgen10 : string := "shishir"; + Vgen11 : bit_vector := B"0011"; + Vgen12 : boolean_vector:= (true,false); + Vgen13 : severity_level_vector := (note,error); + Vgen14 : integer_vector:= (1,2,3,4); + Vgen15 : real_vector := (1.0,2.0,3.0,4.0); + Vgen16 : time_vector := (1 ns, 2 ns, 3 ns, 4 ns); + Vgen17 : natural_vector:= (1,2,3,4); + Vgen18 : positive_vector:= (1,2,3,4) + ); +END c01s01b01x01p05n02i00758ent; + +ARCHITECTURE c01s01b01x01p05n02i00758arch OF c01s01b01x01p05n02i00758ent IS + +BEGIN + assert Vgen1 = C1 report "Initializing signal with generic Vgen1 does not work" severity error; + assert Vgen2 = C2 report "Initializing signal with generic Vgen2 does not work" severity error; + assert Vgen3 = C3 report "Initializing signal with generic Vgen3 does not work" severity error; + assert Vgen4 = C4 report "Initializing signal with generic Vgen4 does not work" severity error; + assert Vgen5 = C5 report "Initializing signal with generic Vgen5 does not work" severity error; + assert Vgen6 = C6 report "Initializing signal with generic Vgen6 does not work" severity error; + assert Vgen7 = C7 report "Initializing signal with generic Vgen7 does not work" severity error; + assert Vgen8 = C8 report "Initializing signal with generic Vgen8 does not work" severity error; + assert Vgen9 = C9 report "Initializing signal with generic Vgen9 does not work" severity error; + assert Vgen10 = C10 report "Initializing signal with generic Vgen10 does not work" severity error; + assert Vgen11 = C11 report "Initializing signal with generic Vgen11 does not work" severity error; + assert Vgen12 = C12 report "Initializing signal with generic Vgen12 does not work" severity error; + assert Vgen13 = C13 report "Initializing signal with generic Vgen13 does not work" severity error; + assert Vgen14 = C14 report "Initializing signal with generic Vgen14 does not work" severity error; + assert Vgen15 = C15 report "Initializing signal with generic Vgen15 does not work" severity error; + assert Vgen16 = C16 report "Initializing signal with generic Vgen16 does not work" severity error; + assert Vgen17 = C17 report "Initializing signal with generic Vgen17 does not work" severity error; + assert Vgen18 = C18 report "Initializing signal with generic Vgen18 does not work" severity error; + + TESTING: PROCESS + BEGIN + + assert NOT( Vgen1 = C1 and + Vgen2 = C2 and + Vgen3 = C3 and + Vgen4 = C4 and + Vgen5 = C5 and + Vgen6 = C6 and + Vgen7 = C7 and + Vgen8 = C8 and + Vgen9 = C9 and + Vgen10 = C10 and + Vgen11 = C11 and + Vgen12 = C12 and + Vgen13 = C13 and + Vgen14 = C14 and + Vgen15 = C15 and + Vgen16 = C16 and + Vgen17 = C17 and + Vgen18 = C18 ) + report "***PASSED TEST: c01s01b01x01p05n02i00758" + severity NOTE; + assert( Vgen1 = C1 and + Vgen2 = C2 and + Vgen3 = C3 and + Vgen4 = C4 and + Vgen5 = C5 and + Vgen6 = C6 and + Vgen7 = C7 and + Vgen8 = C8 and + Vgen9 = C9 and + Vgen10 = C10 and + Vgen11 = C11 and + Vgen12 = C12 and + Vgen13 = C13 and + Vgen14 = C14 and + Vgen15 = C15 and + Vgen16 = C16 and + Vgen17 = C17 and + Vgen18 = C18 ) + report "***FAILED TEST: c01s01b01x01p05n02i00758 - Generic can be used to specify the size of ports." + severity ERROR; + wait; + END PROCESS TESTING; + +END c01s01b01x01p05n02i00758arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc814.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc814.vhd new file mode 100644 index 0000000..7b526e6 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc814.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc814.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c01s02b00x00p04n02i00814ent IS +END c01s02b00x00p04n02i00814ent; + +ARCHITECTURE c01s02b00x00p04n02i00814arch OF c01s02b00x00p04n02i00814ent IS + +BEGIN + TESTING: PROCESS + BEGIN + assert FALSE + report "***FAILED TEST: c01s02b00x00p04n02i00814 - Entity declaration and architecture body must reside in the same library." + severity ERROR; + wait; + END PROCESS TESTING; + +END c01s02b00x00p04n02i00814arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc816.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc816.vhd new file mode 100644 index 0000000..e8f634b --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc816.vhd @@ -0,0 +1,57 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc816.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c01s02b00x00p06n01i00816ent IS +END c01s02b00x00p06n01i00816ent; + +ARCHITECTURE c01s02b00x00p06n01i00816arch OF c01s02b00x00p06n01i00816ent IS + +BEGIN + TESTING: PROCESS + BEGIN + assert FALSE + report "***PASSED TEST: c01s02b00x00p06n01i00816" + severity NOTE; + wait; + END PROCESS TESTING; + +END c01s02b00x00p06n01i00816arch; + + +ARCHITECTURE c01s02b00x00p06n01i00816arch_2 OF c01s02b00x00p06n01i00816ent IS + +BEGIN + TESTING: PROCESS + BEGIN + null; + wait; + END PROCESS TESTING; + +END c01s02b00x00p06n01i00816arch_2; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc833.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc833.vhd new file mode 100644 index 0000000..b881fb1 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc833.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc833.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +ENTITY c01s03b00x00p05n02i00833ent IS +END c01s03b00x00p05n02i00833ent; + +ARCHITECTURE c01s03b00x00p05n02i00833arch OF c01s03b00x00p05n02i00833ent IS + +BEGIN + TESTING: PROCESS + BEGIN +-- assert FALSE +-- report "***FAILED TEST: c01s03b00x00p05n02i00833 - Configuration declaration and corresponding entity declaration must reside in the same library." +-- severity ERROR; + wait; + END PROCESS TESTING; + +END c01s03b00x00p05n02i00833arch; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd new file mode 100644 index 0000000..f580da2 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc851.vhd @@ -0,0 +1,291 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc851.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c01s03b01x00p12n01i00851pkg_b is + constant zero : integer ; + constant one : integer ; + constant two : integer ; + constant three: integer ; + constant four : integer ; + constant five : integer ; + constant six : integer ; + constant seven: integer ; + constant eight: integer ; + constant nine : integer ; + constant fifteen: integer; +end c01s03b01x00p12n01i00851pkg_b; + +package body c01s03b01x00p12n01i00851pkg_b is + constant zero : integer := 0; + constant one : integer := 1; + constant two : integer := 2; + constant three: integer := 3; + constant four : integer := 4; + constant five : integer := 5; + constant six : integer := 6; + constant seven: integer := 7; + constant eight: integer := 8; + constant nine : integer := 9; + constant fifteen:integer:= 15; +end c01s03b01x00p12n01i00851pkg_b; + +use work.c01s03b01x00p12n01i00851pkg_b.all; +package c01s03b01x00p12n01i00851pkg_a is + constant low_number : integer := 0; + constant hi_number : integer := 3; + subtype hi_to_low_range is integer range low_number to hi_number; + type boolean_vector is array (natural range <>) of boolean; + type severity_level_vector is array (natural range <>) of severity_level; + type integer_vector is array (natural range <>) of integer; + type real_vector is array (natural range <>) of real; + type time_vector is array (natural range <>) of time; + type natural_vector is array (natural range <>) of natural; + type positive_vector is array (natural range <>) of positive; + type record_std_package is record + a: boolean; + b: bit; + c:character; + d:severity_level; + e:integer; + f:real; + g:time; + h:natural; + i:positive; + end record; + type array_rec_std is array (natural range <>) of record_std_package; + type four_value is ('Z','0','1','X'); +--enumerated type + constant C1 : boolean := true; + constant C2 : bit := '1'; + constant C3 : character := 's'; + constant C4 : severity_level := note; + constant C5 : integer := 3; + constant C6 : real := 3.0; + constant C7 : time := 3 ns; + constant C8 : natural := 1; + constant C9 : positive := 1; + signal Sin1 : bit_vector(zero to five) ; + signal Sin2 : boolean_vector(zero to five) ; + signal Sin4 : severity_level_vector(zero to five) ; + signal Sin5 : integer_vector(zero to five) ; + signal Sin6 : real_vector(zero to five) ; + signal Sin7 : time_vector(zero to five) ; + signal Sin8 : natural_vector(zero to five) ; + signal Sin9 : positive_vector(zero to five) ; + signal Sin10: array_rec_std(zero to five) ; +end c01s03b01x00p12n01i00851pkg_a; + +use work.c01s03b01x00p12n01i00851pkg_a.all; +use work.c01s03b01x00p12n01i00851pkg_b.all; +entity test is + port( + sigin1 : in boolean ; + sigout1 : out boolean ; + sigin2 : in bit ; + sigout2 : out bit ; + sigin4 : in severity_level ; + sigout4 : out severity_level ; + sigin5 : in integer ; + sigout5 : out integer ; + sigin6 : in real ; + sigout6 : out real ; + sigin7 : in time ; + sigout7 : out time ; + sigin8 : in natural ; + sigout8 : out natural ; + sigin9 : in positive ; + sigout9 : out positive ; + sigin10 : in record_std_package ; + sigout10 : out record_std_package + ); +end; + +architecture test of test is +begin + sigout1 <= sigin1; + sigout2 <= sigin2; + sigout4 <= sigin4; + sigout5 <= sigin5; + sigout6 <= sigin6; + sigout7 <= sigin7; + sigout8 <= sigin8; + sigout9 <= sigin9; + sigout10 <= sigin10; +end; + +configuration testbench of test is + for test + end for; +end; + +use work.c01s03b01x00p12n01i00851pkg_a.all; +use work.c01s03b01x00p12n01i00851pkg_b.all; +ENTITY c01s03b01x00p12n01i00851ent IS +END c01s03b01x00p12n01i00851ent; + +ARCHITECTURE c01s03b01x00p12n01i00851arch OF c01s03b01x00p12n01i00851ent IS + component test + port( + sigin1 : in boolean ; + sigout1 : out boolean ; + sigin2 : in bit ; + sigout2 : out bit ; + sigin4 : in severity_level ; + sigout4 : out severity_level ; + sigin5 : in integer ; + sigout5 : out integer ; + sigin6 : in real ; + sigout6 : out real ; + sigin7 : in time ; + sigout7 : out time ; + sigin8 : in natural ; + sigout8 : out natural ; + sigin9 : in positive ; + sigout9 : out positive ; + sigin10 : in record_std_package ; + sigout10 : out record_std_package + ); + end component; +begin + Sin1(zero) <='1'; + Sin2(zero) <= true; + Sin4(zero) <= note; + Sin5(zero) <= 3; + Sin6(zero) <= 3.0; + Sin7(zero) <= 3 ns; + Sin8(zero) <= 1; + Sin9(zero) <= 1; + Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); + K:block + component test + port( + sigin1 : in boolean ; + sigout1 : out boolean ; + sigin2 : in bit ; + sigout2 : out bit ; + sigin4 : in severity_level ; + sigout4 : out severity_level ; + sigin5 : in integer ; + sigout5 : out integer ; + sigin6 : in real ; + sigout6 : out real ; + sigin7 : in time ; + sigout7 : out time ; + sigin8 : in natural ; + sigout8 : out natural ; + sigin9 : in positive ; + sigout9 : out positive ; + sigin10 : in record_std_package ; + sigout10 : out record_std_package + ); + end component; + + BEGIN + T5 : test + port map + ( + Sin2(4),Sin2(5), + Sin1(4),Sin1(5), + Sin4(4),Sin4(5), + Sin5(4),Sin5(5), + Sin6(4),Sin6(5), + Sin7(4),Sin7(5), + Sin8(4),Sin8(5), + Sin9(4),Sin9(5), + Sin10(4),Sin10(5) + ); + G: for i in zero to three generate + T1:test + port map + ( + Sin2(i),Sin2(i+1), + Sin1(i),Sin1(i+1), + Sin4(i),Sin4(i+1), + Sin5(i),Sin5(i+1), + Sin6(i),Sin6(i+1), + Sin7(i),Sin7(i+1), + Sin8(i),Sin8(i+1), + Sin9(i),Sin9(i+1), + Sin10(i),Sin10(i+1) + ); + end generate; + end block; + TESTING: PROCESS + BEGIN + wait for 1 ns; + assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; + assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; + assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; + assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; + assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; + assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; + assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; + assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; + assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; + assert NOT( Sin1(0) = sin1(5) and + Sin2(0) = Sin2(5) and + Sin4(0) = Sin4(5) and + Sin5(0) = Sin5(5) and + Sin6(0) = Sin6(5) and + Sin7(0) = Sin7(5) and + Sin8(0) = Sin8(5) and + Sin9(0) = Sin9(5) and + Sin10(0)= Sin10(0) ) + report "***PASSED TEST: c01s03b01x00p12n01i00851" + severity NOTE; + assert ( Sin1(0) = sin1(5) and + Sin2(0) = Sin2(5) and + Sin4(0) = Sin4(5) and + Sin5(0) = Sin5(5) and + Sin6(0) = Sin6(5) and + Sin7(0) = Sin7(5) and + Sin8(0) = Sin8(5) and + Sin9(0) = Sin9(5) and + Sin10(0)= Sin10(0) ) + report "***FAILED TEST: c01s03b01x00p12n01i00851 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." + severity ERROR; + wait; + END PROCESS TESTING; + +END c01s03b01x00p12n01i00851arch; + +configuration c01s03b01x00p12n01i00851cfg of c01s03b01x00p12n01i00851ent is + for c01s03b01x00p12n01i00851arch + for K + for T5:test use configuration work.testbench; + end for; + for G(three downto zero) + for T1:test + use configuration work.testbench; + end for; + end for; + end for; + end for; +end; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd new file mode 100644 index 0000000..840368f --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc865.vhd @@ -0,0 +1,278 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc865.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +package c01s03b01x00p12n01i00865pkg is + constant low_number : integer := 0; + constant hi_number : integer := 3; + subtype hi_to_low_range is integer range low_number to hi_number; + type boolean_vector is array (natural range <>) of boolean; + type severity_level_vector is array (natural range <>) of severity_level; + type integer_vector is array (natural range <>) of integer; + type real_vector is array (natural range <>) of real; + type time_vector is array (natural range <>) of time; + type natural_vector is array (natural range <>) of natural; + type positive_vector is array (natural range <>) of positive; + type record_std_package is record + a: boolean; + b: bit; + c:character; + d:severity_level; + e:integer; + f:real; + g:time; + h:natural; + i:positive; + end record; + type array_rec_std is array (natural range <>) of record_std_package; + type four_value is ('Z','0','1','X'); +--enumerated type + constant C1 : boolean := true; + constant C2 : bit := '1'; + constant C3 : character := 's'; + constant C4 : severity_level := note; + constant C5 : integer := 3; + constant C6 : real := 3.0; + constant C7 : time := 3 ns; + constant C8 : natural := 1; + constant C9 : positive := 1; + signal dumy : bit_vector(0 to 3); + signal Sin1 : bit_vector(0 to 5) ; + signal Sin2 : boolean_vector(0 to 5) ; + signal Sin4 : severity_level_vector(0 to 5) ; + signal Sin5 : integer_vector(0 to 5) ; + signal Sin6 : real_vector(0 to 5) ; + signal Sin7 : time_vector(0 to 5) ; + signal Sin8 : natural_vector(0 to 5) ; + signal Sin9 : positive_vector(0 to 5) ; + signal Sin10: array_rec_std(0 to 5) ; +end c01s03b01x00p12n01i00865pkg; + +use work.c01s03b01x00p12n01i00865pkg.all; +entity test is + port( + sigin1 : in boolean ; + sigout1 : out boolean ; + sigin2 : in bit ; + sigout2 : out bit ; + sigin4 : in severity_level ; + sigout4 : out severity_level ; + sigin5 : in integer ; + sigout5 : out integer ; + sigin6 : in real ; + sigout6 : out real ; + sigin7 : in time ; + sigout7 : out time ; + sigin8 : in natural ; + sigout8 : out natural ; + sigin9 : in positive ; + sigout9 : out positive ; + sigin10 : in record_std_package ; + sigout10 : out record_std_package + ); +end; + +architecture test of test is +begin + sigout1 <= sigin1; + sigout2 <= sigin2; + sigout4 <= sigin4; + sigout5 <= sigin5; + sigout6 <= sigin6; + sigout7 <= sigin7; + sigout8 <= sigin8; + sigout9 <= sigin9; + sigout10 <= sigin10; +end; + +configuration testbench of test is + for test + end for; +end; + +use work.c01s03b01x00p12n01i00865pkg.all; +ENTITY c01s03b01x00p12n01i00865ent IS + generic( + zero : integer := 0; + one : integer := 1; + two : integer := 2; + three: integer := 3; + four : integer := 4; + five : integer := 5; + six : integer := 6; + seven: integer := 7; + eight: integer := 8; + nine : integer := 9; + fifteen:integer:= 15); +END c01s03b01x00p12n01i00865ent; + +ARCHITECTURE c01s03b01x00p12n01i00865arch OF c01s03b01x00p12n01i00865ent IS + component test + port( + sigin1 : in boolean ; + sigout1 : out boolean ; + sigin2 : in bit ; + sigout2 : out bit ; + sigin4 : in severity_level ; + sigout4 : out severity_level ; + sigin5 : in integer ; + sigout5 : out integer ; + sigin6 : in real ; + sigout6 : out real ; + sigin7 : in time ; + sigout7 : out time ; + sigin8 : in natural ; + sigout8 : out natural ; + sigin9 : in positive ; + sigout9 : out positive ; + sigin10 : in record_std_package ; + sigout10 : out record_std_package + ); + end component; +begin + Sin1(zero) <='1'; + Sin2(zero) <= true; + Sin4(zero) <= note; + Sin5(zero) <= 3; + Sin6(zero) <= 3.0; + Sin7(zero) <= 3 ns; + Sin8(zero) <= 1; + Sin9(zero) <= 1; + Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); + K:block + component test + port( + sigin1 : in boolean ; + sigout1 : out boolean ; + sigin2 : in bit ; + sigout2 : out bit ; + sigin4 : in severity_level ; + sigout4 : out severity_level ; + sigin5 : in integer ; + sigout5 : out integer ; + sigin6 : in real ; + sigout6 : out real ; + sigin7 : in time ; + sigout7 : out time ; + sigin8 : in natural ; + sigout8 : out natural ; + sigin9 : in positive ; + sigout9 : out positive ; + sigin10 : in record_std_package ; + sigout10 : out record_std_package + ); + end component; + + BEGIN + T5 : test + port map + ( + Sin2(4),Sin2(5), + Sin1(4),Sin1(5), + Sin4(4),Sin4(5), + Sin5(4),Sin5(5), + Sin6(4),Sin6(5), + Sin7(4),Sin7(5), + Sin8(4),Sin8(5), + Sin9(4),Sin9(5), + Sin10(4),Sin10(5) + ); + G: for i in zero to three generate + T1:test + port map + ( + Sin2(i),Sin2(i+1), + Sin1(i),Sin1(i+1), + Sin4(i),Sin4(i+1), + Sin5(i),Sin5(i+1), + Sin6(i),Sin6(i+1), + Sin7(i),Sin7(i+1), + Sin8(i),Sin8(i+1), + Sin9(i),Sin9(i+1), + Sin10(i),Sin10(i+1) + ); + end generate; + end block; + TESTING: PROCESS + BEGIN + wait for 1 ns; + assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; + assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; + assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; + assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; + assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; + assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; + assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; + assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; + assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; + assert NOT( Sin1(0) = sin1(5) and + Sin2(0) = Sin2(5) and + Sin4(0) = Sin4(5) and + Sin5(0) = Sin5(5) and + Sin6(0) = Sin6(5) and + Sin7(0) = Sin7(5) and + Sin8(0) = Sin8(5) and + Sin9(0) = Sin9(5) and + Sin10(0)= Sin10(0) ) + report "***PASSED TEST: c01s03b01x00p12n01i00865" + severity NOTE; + assert ( Sin1(0) = sin1(5) and + Sin2(0) = Sin2(5) and + Sin4(0) = Sin4(5) and + Sin5(0) = Sin5(5) and + Sin6(0) = Sin6(5) and + Sin7(0) = Sin7(5) and + Sin8(0) = Sin8(5) and + Sin9(0) = Sin9(5) and + Sin10(0)= Sin10(0) ) + report "***FAILED TEST: c01s03b01x00p12n01i00865 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." + severity ERROR; + wait; + END PROCESS TESTING; + +END c01s03b01x00p12n01i00865arch; + +configuration c01s03b01x00p12n01i00865cfg of c01s03b01x00p12n01i00865ent is + for c01s03b01x00p12n01i00865arch + for K + for T5:test use configuration work.testbench; + end for; + for G(zero to one) + for T1:test + use configuration work.testbench; + end for; + end for; + for G(three downto two) + for T1:test + use configuration work.testbench; + end for; + end for; + end for; + end for; +end; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc882.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc882.vhd new file mode 100644 index 0000000..8f46577 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc882.vhd @@ -0,0 +1,97 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc882.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +entity c10s01b00x00p07n01i00882ent_a is + generic ( + GS1: INTEGER := 3; + GS2: INTEGER := 9 + ); + port ( + PS1: out INTEGER; + PS2: out INTEGER + ); +end c10s01b00x00p07n01i00882ent_a; + +architecture c10s01b00x00p07n01i00882arch_a of c10s01b00x00p07n01i00882ent_a is + +begin + process + begin + PS1 <= GS1 + 1; + PS2 <= GS2 + 2; + wait; -- forever + end process; +end c10s01b00x00p07n01i00882arch_a; + +use WORK.c10s01b00x00p07n01i00882ent_a; +ENTITY c10s01b00x00p07n01i00882ent IS +END c10s01b00x00p07n01i00882ent; + +ARCHITECTURE c10s01b00x00p07n01i00882arch OF c10s01b00x00p07n01i00882ent IS + + signal G1: INTEGER; + signal G2: INTEGER; + signal A : INTEGER; + signal B : INTEGER; + component c10s01b00x00p07n01i00882ent_a + generic ( G1, G2: INTEGER ); + port ( A, B: out INTEGER ); + end component; + signal S1: INTEGER; + signal S2: INTEGER; + +BEGIN + + A1: c10s01b00x00p07n01i00882ent_a generic map ( 3, 9 ) port map ( S1, S2 ); + + -- verification + TESTING: PROCESS + BEGIN + wait for 5 ns; + assert NOT( S1=4 and S2=11 ) + report "***PASSED TEST: c10s01b00x00p07n01i00882" + severity NOTE; + assert ( S1=4 and S2=11 ) + report "***FAILED TEST: c10s01b00x00p07n01i00882 - A declarative region is formed by the text of a component declaration." + severity ERROR; + wait; + END PROCESS TESTING; + +END c10s01b00x00p07n01i00882arch; + +configuration c10s01b00x00p07n01i00882cfg of c10s01b00x00p07n01i00882ent is + for c10s01b00x00p07n01i00882arch + for A1: c10s01b00x00p07n01i00882ent_a + use entity c10s01b00x00p07n01i00882ent_a (c10s01b00x00p07n01i00882arch_a ) + generic map ( G1, G2 ) + port map ( A, B ); + end for; + end for; +end c10s01b00x00p07n01i00882cfg; diff --git a/testsuite/vests/vhdl-93/billowitch/disputed/tc996.vhd b/testsuite/vests/vhdl-93/billowitch/disputed/tc996.vhd new file mode 100644 index 0000000..cd08a71 --- /dev/null +++ b/testsuite/vests/vhdl-93/billowitch/disputed/tc996.vhd @@ -0,0 +1,200 @@ + +-- Copyright (C) 2001 Bill Billowitch. + +-- Some of the work to develop this test suite was done with Air Force +-- support. The Air Force and Bill Billowitch assume no +-- responsibilities for this software. + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: tc996.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $ +-- $Revision: 1.2 $ +-- +-- --------------------------------------------------------------------- + +-- too mangled up to fix for me + +PACKAGE c06s03b00x00p08n01i00996pkg IS +-- +-- This packages contains declarations of User attributes +-- +-- ---------------------------------------------------------------------- +-- + TYPE RESISTANCE IS RANGE 0 TO 1E9 + UNITS + pf; + nf = 1000 pf; + mf = 1000 nf; + END UNITS; + + TYPE t_logic IS ( + U, D, + Z0, Z1, ZDX, DZX, ZX, + W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX, + R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX, + F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX + ); +-- +-- Scalar types Declarations +-- + SUBTYPE st_scl1 IS BOOLEAN; + SUBTYPE st_scl2 IS BIT; + SUBTYPE st_scl3 IS CHARACTER; + SUBTYPE st_scl4 IS INTEGER; + SUBTYPE st_scl5 IS REAL; + SUBTYPE st_scl6 IS TIME; + SUBTYPE st_scl7 IS RESISTANCE; + SUBTYPE st_scl8 IS t_logic; +-- +-- character string types +-- + SUBTYPE st_str1 IS STRING; + SUBTYPE st_str2 IS STRING (1 TO 4); + +-- --------------------------------------------------------------------- +-- Attribute Declarations +-- --------------------------------------------------------------------- +-- + ATTRIBUTE atr_scl1 : st_scl1; + ATTRIBUTE atr_scl2 : st_scl2; + ATTRIBUTE atr_scl3 : st_scl3; + ATTRIBUTE atr_scl4 : st_scl4; + ATTRIBUTE atr_scl5 : st_scl5; + ATTRIBUTE atr_scl6 : st_scl6; + ATTRIBUTE atr_scl7 : st_scl7; + ATTRIBUTE atr_scl8 : st_scl8; + ATTRIBUTE atr_str1 : st_str1; + ATTRIBUTE atr_str2 : st_str2; + +END; + +USE WORK.c06s03b00x00p08n01i00996pkg.all; +ENTITY c06s03b00x00p08n01i00996ent IS + GENERIC ( + p_scl1 : st_scl1; + p_scl2 : st_scl2; + p_scl3 : st_scl3; + p_scl4 : st_scl4; + p_scl5 : st_scl5; + p_scl6 : st_scl6; + p_scl7 : st_scl7; + p_scl8 : st_scl8; + p_str1 : st_str1; + p_str2 : st_str2; + labelid : STRING ); +END c06s03b00x00p08n01i00996ent; + +ARCHITECTURE c06s03b00x00p08n01i00996arch OF c06s03b00x00p08n01i00996ent IS +-- This entity behavior checks the values of attributes referenced at the configuration. +BEGIN + PROCESS + BEGIN + ASSERT p_scl1 = TRUE + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl1" SEVERITY FAILURE; + ASSERT p_scl2 = '0' + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl2" SEVERITY FAILURE; + ASSERT p_scl3 = 'z' + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl3" SEVERITY FAILURE; + ASSERT p_scl4 = 0 + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl4" SEVERITY FAILURE; + ASSERT p_scl5 = 10.0 + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl5" SEVERITY FAILURE; + ASSERT p_scl6 = 10 ns + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl6" SEVERITY FAILURE; + ASSERT p_scl7 = 10000 pf + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl7" SEVERITY FAILURE; + ASSERT p_scl8 = FX + REPORT "ERROR: Wrong value for " & labelid & "'atr_scl8" SEVERITY FAILURE; + ASSERT p_str1 = "signal" + REPORT "ERROR: Wrong value for " & labelid & "'atr_str1" SEVERITY FAILURE; + ASSERT p_str2 = "XXXX" + REPORT "ERROR: Wrong value for " & labelid & "'atr_str2" SEVERITY FAILURE; + + assert NOT( p_scl1 = TRUE + and p_scl2 = '0' + and p_scl3 = 'z' + and p_scl4 = 0 + and p_scl5 = 10.0 + and p_scl6 = 10 ns + and p_scl7 = 10000 pf + and p_scl8 = FX + and p_str1 = "signal" + and p_str2 = "XXXX") + report "***PASSED TEST: c06s03b00x00p08n01i00996" + severity NOTE; + assert ( p_scl1 = TRUE + and p_scl2 = '0' + and p_scl3 = 'z' + and p_scl4 = 0 + and p_scl5 = 10.0 + and p_scl6 = 10 ns + and p_scl7 = 10000 pf + and p_scl8 = FX + and p_str1 = "signal" + and p_str2 = "XXXX") + report "***FAILED TEST: c06s03b00x00p08n01i00996 - Expanded name denotes a primary unit contained in design library test failed." + severity ERROR; + wait; + END PROCESS; +END; + + +USE WORK.c06s03b00x00p08n01i00996pkg.all; +ENTITY c06s03b00x00p08n01i00996ent_a IS +END c06s03b00x00p08n01i00996ent_a; + +ARCHITECTURE c06s03b00x00p08n01i00996arch OF c06s03b00x00p08n01i00996ent IS +-- + COMPONENT c06s03b00x00p08n01i00996ent_a + END COMPONENT; + +BEGIN + check : c06s03b00x00p08n01i00996ent_a; +END c06s03b00x00p08n01i00996arch; + +USE WORK.c06s03b00x00p08n01i00996pkg.all; +CONFIGURATION c06s03b00x00p08n01i00996cfg OF c06s03b00x00p08n01i00996ent IS + ATTRIBUTE atr_scl1 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS TRUE; + ATTRIBUTE atr_scl2 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS '0'; + ATTRIBUTE atr_scl3 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS 'z'; + ATTRIBUTE atr_scl4 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS 0; + ATTRIBUTE atr_scl5 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS 10.0; + ATTRIBUTE atr_scl6 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS 10 ns; + ATTRIBUTE atr_scl7 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS 10000 pf; + ATTRIBUTE atr_scl8 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS FX; + ATTRIBUTE atr_str1 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS "signal"; + ATTRIBUTE atr_str2 OF c06s03b00x00p08n01i00996cfg: CONFIGURATION IS "XXXX"; + + FOR c06s03b00x00p08n01i00996arch + FOR check : c06s03b00x00p08n01i00996ent_a USE ENTITY WORK.c06s03b00x00p08n01i00996ent_a(c06s03b00x00p08n01i00996arch_a) + GENERIC MAP ( + c06s03b00x00p08n01i00996cfg'atr_scl1, + c06s03b00x00p08n01i00996cfg'atr_scl2, + c06s03b00x00p08n01i00996cfg'atr_scl3, + c06s03b00x00p08n01i00996cfg'atr_scl4, + c06s03b00x00p08n01i00996cfg'atr_scl5, + c06s03b00x00p08n01i00996cfg'atr_scl6, + c06s03b00x00p08n01i00996cfg'atr_scl7, + c06s03b00x00p08n01i00996cfg'atr_scl8, + c06s03b00x00p08n01i00996cfg'atr_str1, + c06s03b00x00p08n01i00996cfg'atr_str2, + "work.c06s03b00x00p08n01i00996cfg" ); + END FOR; + END FOR; +END c06s03b00x00p08n01i00996cfg; |