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author | Tristan Gingold | 2015-09-26 05:55:02 +0200 |
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committer | Tristan Gingold | 2015-09-26 05:55:02 +0200 |
commit | 2eecd0d0a22dc22c7c52eeff9a91bef2a6b2bb5c (patch) | |
tree | a0c6124ff89a0e33bf4a73a6dc6ca0cf56becea2 /testsuite/gna/ticket94/tb4.vhd | |
parent | a3dbf28891487f13726061f607c3cd62e5f69e1e (diff) | |
download | ghdl-2eecd0d0a22dc22c7c52eeff9a91bef2a6b2bb5c.tar.gz ghdl-2eecd0d0a22dc22c7c52eeff9a91bef2a6b2bb5c.tar.bz2 ghdl-2eecd0d0a22dc22c7c52eeff9a91bef2a6b2bb5c.zip |
ticket94 reproducer
Diffstat (limited to 'testsuite/gna/ticket94/tb4.vhd')
-rw-r--r-- | testsuite/gna/ticket94/tb4.vhd | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/gna/ticket94/tb4.vhd b/testsuite/gna/ticket94/tb4.vhd new file mode 100644 index 0000000..d981701 --- /dev/null +++ b/testsuite/gna/ticket94/tb4.vhd @@ -0,0 +1,31 @@ + +library ieee; +use ieee.std_logic_1164.all; +library alib; + +entity tb4 is +end; + +architecture arch of tb4 is + + signal a, b : std_logic := '0'; + component acomp is + port (x: in std_ulogic; y: out std_ulogic); + end component; + +begin + ainst: acomp + port map (a, b); + + process is + begin + a <= '0'; + wait for 1 ns; + assert b = '0' report "component is missing" severity failure; + a <= '1'; + wait for 1 ns; + assert b = '1' report "component is missing" severity failure; + wait; + end process; + +end architecture; |