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authorTristan Gingold2015-05-20 06:57:45 +0200
committerTristan Gingold2015-05-20 06:57:45 +0200
commit4528ed26b1b22562a4552368459f5d5acf5c3847 (patch)
tree082d3567d8b547f385f5865b5f690fc6e1c5b61a /testsuite/gna/ticket71/bug.vhdl
parent34c5b03cc0c5958d4ddfbea2ea6aaae6ed30f5fd (diff)
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Testcase for ticket 71.
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1 files changed, 43 insertions, 0 deletions
diff --git a/testsuite/gna/ticket71/bug.vhdl b/testsuite/gna/ticket71/bug.vhdl
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+package pkg is
+ procedure proc(signal sig : in integer; msg : string);
+end package;
+
+package body pkg is
+ procedure proc(signal sig : in integer; msg : string) is
+ begin
+ loop
+ wait on sig;
+ report integer'image(sig) & " : " & msg;
+ end loop;
+ end procedure;
+end package body;
+
+use work.pkg.all;
+
+entity ent2 is
+ port (
+ prt : out integer);
+begin
+ proc(prt, "entity");
+end entity;
+
+architecture a of ent2 is
+begin
+ proc(prt, "architecture");
+ main : process
+ begin
+ prt <= 1;
+ wait for 1 ns;
+ prt <= 2;
+ wait;
+ end process;
+end architecture;
+
+entity ent is
+end entity;
+
+architecture a of ent is
+ signal sig : integer;
+begin
+ ent2_inst : entity work.ent2 port map(prt => sig);
+end architecture;