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authorTristan Gingold2014-12-07 11:40:58 +0100
committerTristan Gingold2014-12-07 11:40:58 +0100
commit2f4337f027ec97dd93642ea2db70873e9192fb3b (patch)
treed8c63b4cef84e33bae4e7018ce7abc07e0e3bd3c /testsuite/gna/perf02/add_159.vhd
parentabe17103c669922a7349a7b2238d440b24d29f30 (diff)
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Add perf02 (performance issue).
Diffstat (limited to 'testsuite/gna/perf02/add_159.vhd')
-rw-r--r--testsuite/gna/perf02/add_159.vhd33
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diff --git a/testsuite/gna/perf02/add_159.vhd b/testsuite/gna/perf02/add_159.vhd
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+library ieee;
+use ieee.std_logic_1164.all;
+
+library ieee;
+use ieee.numeric_std.all;
+
+entity add_159 is
+ port (
+ output : out std_logic_vector(31 downto 0);
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0)
+ );
+end add_159;
+
+architecture augh of add_159 is
+
+ signal carry_inA : std_logic_vector(33 downto 0);
+ signal carry_inB : std_logic_vector(33 downto 0);
+ signal carry_res : std_logic_vector(33 downto 0);
+
+begin
+
+ -- To handle the CI input, the operation is '1' + CI
+ -- If CI is not present, the operation is '1' + '0'
+ carry_inA <= '0' & in_a & '1';
+ carry_inB <= '0' & in_b & '0';
+ -- Compute the result
+ carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
+
+ -- Set the outputs
+ output <= carry_res(32 downto 1);
+
+end architecture;