summaryrefslogtreecommitdiff
path: root/testsuite/gna/bug17759
diff options
context:
space:
mode:
authorTristan Gingold2014-01-05 17:09:57 +0100
committerTristan Gingold2014-01-05 17:09:57 +0100
commit6db77714c4d66adfb58872d05c8e3aaef55c7e00 (patch)
treecdf847208b82a3f4e8143f9931063a24aff885db /testsuite/gna/bug17759
parent6ab63305d08ac83573aeb65bfd4dd266b8ad9aed (diff)
downloadghdl-6db77714c4d66adfb58872d05c8e3aaef55c7e00.tar.gz
ghdl-6db77714c4d66adfb58872d05c8e3aaef55c7e00.tar.bz2
ghdl-6db77714c4d66adfb58872d05c8e3aaef55c7e00.zip
Fix bug17759: individual associated to an element of array of array.
Diffstat (limited to 'testsuite/gna/bug17759')
-rw-r--r--testsuite/gna/bug17759/test.vhdl43
-rwxr-xr-xtestsuite/gna/bug17759/testsuite.sh10
2 files changed, 53 insertions, 0 deletions
diff --git a/testsuite/gna/bug17759/test.vhdl b/testsuite/gna/bug17759/test.vhdl
new file mode 100644
index 0000000..8f019b3
--- /dev/null
+++ b/testsuite/gna/bug17759/test.vhdl
@@ -0,0 +1,43 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package test is
+ type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
+end package test;
+
+
+use work.test.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity b is
+ port (io_a : inout array_t);
+end entity b;
+
+architecture rtl of b is
+begin -- architecture dummy
+ io_a <= ("HH", "LL");
+end architecture rtl;
+
+
+use work.test.all;
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity a is
+ port (io_v : inout std_logic_vector(1 downto 0);
+ io_1 : inout std_logic;
+ io_2 : inout std_logic);
+end entity a;
+
+architecture rtl of a is
+ component b is
+ port (io_a : inout array_t);
+ end component b;
+begin -- architecture rtl
+ b1 : b port map (
+ io_a(0) => io_v,
+ io_a(1)(0) => io_1,
+ io_a(1)(1) => io_2);
+end architecture rtl;
diff --git a/testsuite/gna/bug17759/testsuite.sh b/testsuite/gna/bug17759/testsuite.sh
new file mode 100755
index 0000000..3de908b
--- /dev/null
+++ b/testsuite/gna/bug17759/testsuite.sh
@@ -0,0 +1,10 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+analyze test.vhdl
+elab_simulate a
+
+clean
+
+echo "Test successful"