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authorTristan Gingold2015-01-22 05:09:37 +0100
committerTristan Gingold2015-01-22 05:09:37 +0100
commite18db47d92bb735f782e4409abb77d7b9233672f (patch)
treec17431465d3840ce1d3bb0588987f8ca66a8de38 /testsuite/gna/bug09/univ1.vhdl
parent34e81c81b0a32d0974617672f2087fceeaba80a0 (diff)
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Add bug09 testcase on time<->univ_integer conversions.
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diff --git a/testsuite/gna/bug09/univ1.vhdl b/testsuite/gna/bug09/univ1.vhdl
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+entity univ1 is
+end entity;
+
+architecture foo of univ1 is
+ signal i: integer := Time'POS(Time'High); -- should produce error
+
+ -- 6.4.2.3 Signal declarations, para 5, first sentence:
+ -- If the signal declaration includes the assignment symbol followed by an
+ -- expression, it shall be of the same type as the signal. Such an
+ -- expression is said to be a default expression.
+ --
+ -- -1993 4.3.1.2 Signal declarations, para 6, first sentence:
+ -- If the signal declaration includes the assignment symbol followed by
+ -- an expression, it must be of the same type as the signal.
+
+ -- 'POS returns universal integer
+ --
+begin
+ assert False
+ report "i = " & integer'IMAGE(i) -- shows left clipping instead of error
+ severity ERROR;
+end architecture; \ No newline at end of file