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author | Tristan Gingold | 2015-06-02 20:21:32 +0200 |
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committer | Tristan Gingold | 2015-06-02 20:21:32 +0200 |
commit | 3e6affe81ae722794a3d74e0a480c7d9dacdf406 (patch) | |
tree | c78b03e04ac761b40279b6838425be2f1b57e5ae /src/vhdl | |
parent | d82c1416e7e247023f171aea8855f8a2cac5397c (diff) | |
download | ghdl-3e6affe81ae722794a3d74e0a480c7d9dacdf406.tar.gz ghdl-3e6affe81ae722794a3d74e0a480c7d9dacdf406.tar.bz2 ghdl-3e6affe81ae722794a3d74e0a480c7d9dacdf406.zip |
Fix simulate backend.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/simulate/debugger.adb | 7 | ||||
-rw-r--r-- | src/vhdl/simulate/elaboration.adb | 2 | ||||
-rw-r--r-- | src/vhdl/simulate/execution.adb | 55 | ||||
-rw-r--r-- | src/vhdl/simulate/simulation.adb | 2 |
4 files changed, 42 insertions, 24 deletions
diff --git a/src/vhdl/simulate/debugger.adb b/src/vhdl/simulate/debugger.adb index 87cef49..b3e7a90 100644 --- a/src/vhdl/simulate/debugger.adb +++ b/src/vhdl/simulate/debugger.adb @@ -848,7 +848,7 @@ package body Debugger is Put (Disp_Node (Instance.Label)); if Instance.Stmt /= Null_Iir then Put (" at "); - Put (Get_Location_Str (Get_Location (Instance.Stmt))); + Put (Files_Map.Image (Get_Location (Instance.Stmt))); end if; New_Line; end Disp_A_Frame; @@ -975,7 +975,7 @@ package body Debugger is procedure Disp_Process_Loc (Proc : Process_State_Type) is begin Disp_Instance_Name (Proc.Top_Instance); - Put (" (" & Get_Location_Str (Get_Location (Proc.Proc)) & ")"); + Put (" (" & Files_Map.Image (Get_Location (Proc.Proc)) & ")"); New_Line; end Disp_Process_Loc; @@ -1039,8 +1039,7 @@ package body Debugger is procedure Set_Breakpoint (Stmt : Iir) is begin - Put_Line - ("set breakpoint at: " & Get_Location_Str (Get_Location (Stmt))); + Put_Line ("set breakpoint at: " & Files_Map.Image (Get_Location (Stmt))); Breakpoints.Append (Breakpoint_Entry'(Stmt => Stmt)); Flag_Need_Debug := True; end Set_Breakpoint; diff --git a/src/vhdl/simulate/elaboration.adb b/src/vhdl/simulate/elaboration.adb index 0deb329..18fcd10 100644 --- a/src/vhdl/simulate/elaboration.adb +++ b/src/vhdl/simulate/elaboration.adb @@ -1701,7 +1701,7 @@ package body Elaboration is -- declaration and architecture body or is bound to a configuration of -- such a design entity. if not Is_Fully_Bound (Conf) then - Warning_Msg (Disp_Node (Stmt) & " not bound"); + Warning_Msg_Elab (Disp_Node (Stmt) & " not bound", Stmt); return; end if; diff --git a/src/vhdl/simulate/execution.adb b/src/vhdl/simulate/execution.adb index 41a80ef..c1af588 100644 --- a/src/vhdl/simulate/execution.adb +++ b/src/vhdl/simulate/execution.adb @@ -264,7 +264,7 @@ package body Execution is | Iir_Kind_Enumeration_Subtype_Definition => declare Lits : constant Iir_List := - Get_Enumeration_Literal_List (Expr_Type); + Get_Enumeration_Literal_List (Get_Base_Type (Expr_Type)); Pos : Natural; begin case Val.Kind is @@ -1377,8 +1377,8 @@ package body Execution is end; when others => - Error_Msg ("execute_implicit_function: unimplemented " & - Iir_Predefined_Functions'Image (Func)); + Error_Msg_Elab ("execute_implicit_function: unimplemented " & + Iir_Predefined_Functions'Image (Func), Expr); raise Internal_Error; end case; return Result; @@ -2672,6 +2672,7 @@ package body Execution is Enums : constant Iir_List := Get_Enumeration_Literal_List (Get_Base_Type (Expr_Type)); Enum : Iir; + Lit_Id : Name_Id; Enum_Id : Name_Id; begin -- Remove leading and trailing blanks @@ -2688,22 +2689,40 @@ package body Execution is end if; end loop; - -- Convert to lower case. - for I in Lit_Start .. Lit_End loop - Str_Str (I) := Grt.Values.To_LC (Str_Str (I)); - end loop; + if Str_Str (Lit_Start) = ''' + and then Str_Str (Lit_End) = ''' + and then Lit_End = Lit_Start + 2 + then + -- Enumeration literal. + Lit_Id := Get_Identifier (Str_Str (Lit_Start + 1)); - for I in Natural loop - Enum := Get_Nth_Element (Enums, I); - if Enum = Null_Iir then - Error_Msg_Exec ("incorrect unit name", Expr); - end if; - Enum_Id := Get_Identifier (Enum); - exit when (Get_Name_Length (Enum_Id) = - Natural (Lit_End - Lit_Start + 1)) - and then (Image (Enum_Id) = - String (Str_Str (Lit_Start .. Lit_End))); - end loop; + for I in Natural loop + Enum := Get_Nth_Element (Enums, I); + exit when Enum = Null_Iir; + exit when Get_Identifier (Enum) = Lit_Id; + end loop; + else + -- Literal identifier. + -- Convert to lower case. + for I in Lit_Start .. Lit_End loop + Str_Str (I) := Grt.Values.To_LC (Str_Str (I)); + end loop; + + for I in Natural loop + Enum := Get_Nth_Element (Enums, I); + exit when Enum = Null_Iir; + Enum_Id := Get_Identifier (Enum); + exit when (Get_Name_Length (Enum_Id) = + Natural (Lit_End - Lit_Start + 1)) + and then (Image (Enum_Id) = + String (Str_Str (Lit_Start .. Lit_End))); + end loop; + end if; + + if Enum = Null_Iir then + Error_Msg_Exec + ("incorrect enumeration literal for 'value", Expr); + end if; return Create_Enum_Value (Natural (Get_Enum_Pos (Enum)), Expr_Type); diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index b3a0160..da15b87 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -1616,7 +1616,7 @@ package body Simulation is end loop; if In_Signals /= 0 then - Error_Msg ("top entity should not have inputs signals"); + Error_Msg_Elab ("top entity should not have inputs signals", Entity); -- raise Simulation_Error; end if; |