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authorTristan Gingold2015-12-16 09:38:00 +0100
committerTristan Gingold2015-12-18 17:16:27 +0100
commite8a965f0f42749f7fbcaaee966e24a55fb45d886 (patch)
tree448d507f7074f78e80dd4afe5b983609a08396ca /src/vhdl/translate/trans-chap1.adb
parent4680da5edb910910c4a31438798bff0bc6e51380 (diff)
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Pass signal values to interfaces. 'sigptr' optimization.
Improve simulation speed by about 20%.
Diffstat (limited to 'src/vhdl/translate/trans-chap1.adb')
-rw-r--r--src/vhdl/translate/trans-chap1.adb7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/vhdl/translate/trans-chap1.adb b/src/vhdl/translate/trans-chap1.adb
index 35cbfb0..a3c8233 100644
--- a/src/vhdl/translate/trans-chap1.adb
+++ b/src/vhdl/translate/trans-chap1.adb
@@ -75,15 +75,20 @@ package body Trans.Chap1 is
is
El : Iir;
El_Type : Iir;
+ Default : Iir;
begin
Push_Local_Factory;
+ Default := Null_Iir;
El := Get_Port_Chain (Entity);
while El /= Null_Iir loop
Open_Temp;
El_Type := Get_Type (El);
if not Is_Fully_Constrained_Type (El_Type) then
- Chap5.Elab_Unconstrained_Port (El, Get_Default_Value (El));
+ if Default = Null_Iir then
+ Default := Create_Iir (Iir_Kind_Association_Element_Open);
+ end if;
+ Chap5.Elab_Unconstrained_Port_Bounds (El, Default);
end if;
Chap4.Elab_Signal_Declaration_Storage (El);
Chap4.Elab_Signal_Declaration_Object (El, Entity, False);