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authorTristan Gingold2015-01-10 06:51:02 +0100
committerTristan Gingold2015-01-10 06:51:02 +0100
commit2c498db7b2702d3ad762c5a35c23bb41538331b7 (patch)
treebe271050334c14aed09c29a2d24750829a811430 /src/vhdl/translate/trans-chap1.adb
parent91af32964eb22b8fe42551a1fa48c7637563fa55 (diff)
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vhdl08: block configuration for if-generate statements.
Diffstat (limited to 'src/vhdl/translate/trans-chap1.adb')
-rw-r--r--src/vhdl/translate/trans-chap1.adb6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/vhdl/translate/trans-chap1.adb b/src/vhdl/translate/trans-chap1.adb
index 1f0e7d3..5911e95 100644
--- a/src/vhdl/translate/trans-chap1.adb
+++ b/src/vhdl/translate/trans-chap1.adb
@@ -785,7 +785,8 @@ package body Trans.Chap1 is
when Iir_Kind_Indexed_Name
| Iir_Kind_Slice_Name =>
Block := Get_Named_Entity (Get_Prefix (Block));
- when Iir_Kinds_Denoting_Name =>
+ when Iir_Kinds_Denoting_Name
+ | Iir_Kind_Parenthesis_Name =>
Block := Get_Named_Entity (Block);
when others =>
null;
@@ -797,7 +798,8 @@ package body Trans.Chap1 is
(El, Base_Block, Get_Info (Block));
when Iir_Kind_Generate_Statement_Body =>
case Get_Kind (Get_Parent (Block)) is
- when Iir_Kind_If_Generate_Statement =>
+ when Iir_Kind_If_Generate_Statement
+ | Iir_Kind_If_Generate_Else_Clause =>
Translate_If_Generate_Block_Configuration_Calls
(El, Base_Info);
when Iir_Kind_For_Generate_Statement =>