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| author | Tristan Gingold | 2016-01-27 05:58:56 +0100 |
|---|---|---|
| committer | Tristan Gingold | 2016-01-27 18:49:25 +0100 |
| commit | ed5fdc7c5fee59ad06d3eed78c7505fc22009f95 (patch) | |
| tree | f991c69675cc2b0dc7f1735c5692f51bceecd827 /src/vhdl/simulate/simulation.adb | |
| parent | bbdcad893c34119c56812b9936fbc5e2dcc62f5c (diff) | |
| download | ghdl-ed5fdc7c5fee59ad06d3eed78c7505fc22009f95.tar.gz ghdl-ed5fdc7c5fee59ad06d3eed78c7505fc22009f95.tar.bz2 ghdl-ed5fdc7c5fee59ad06d3eed78c7505fc22009f95.zip | |
Diffstat (limited to 'src/vhdl/simulate/simulation.adb')
| -rw-r--r-- | src/vhdl/simulate/simulation.adb | 42 |
1 files changed, 16 insertions, 26 deletions
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index df4e6b0..7238bf9 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -470,7 +470,8 @@ package body Simulation is | Iir_Value_Access | Iir_Value_Protected | Iir_Value_Quantity - | Iir_Value_Terminal => + | Iir_Value_Terminal + | Iir_Value_Environment => raise Internal_Error; end case; end Assign_Value_To_Signal; @@ -1095,29 +1096,16 @@ package body Simulation is end loop; return; when Iir_Value_Signal => - case Port.Kind is - when Iir_Value_Signal => - -- Here, SIG and PORT are simple signals (not composite). - -- PORT is a source for SIG. - case Mode is - when Connect_Source => - Grt.Signals.Ghdl_Signal_Add_Source - (Sig.Sig, Port.Sig); - when Connect_Effective => - Grt.Signals.Ghdl_Signal_Effective_Value - (Port.Sig, Sig.Sig); - end case; - when Iir_Value_Access - | Iir_Value_File - | Iir_Value_Range - | Iir_Value_Scalars -- FIXME: by value - | Iir_Value_Record - | Iir_Value_Array - | Iir_Value_Protected - | Iir_Value_Quantity - | Iir_Value_Terminal => - -- These cannot be driving value for a signal. - raise Internal_Error; + pragma Assert (Port.Kind = Iir_Value_Signal); + -- Here, SIG and PORT are simple signals (not composite). + -- PORT is a source for SIG. + case Mode is + when Connect_Source => + Grt.Signals.Ghdl_Signal_Add_Source + (Sig.Sig, Port.Sig); + when Connect_Effective => + Grt.Signals.Ghdl_Signal_Effective_Value + (Port.Sig, Sig.Sig); end case; when Iir_Value_E32 => if Mode = Connect_Source then @@ -1246,7 +1234,8 @@ package body Simulation is | Iir_Value_Protected | Iir_Value_Terminal | Iir_Value_Quantity - | Iir_Value_File => + | Iir_Value_File + | Iir_Value_Environment => raise Internal_Error; end case; end Create_Shadow_Signal; @@ -1562,7 +1551,8 @@ package body Simulation is | Iir_Value_Access | Iir_Value_Protected | Iir_Value_Quantity - | Iir_Value_Terminal => + | Iir_Value_Terminal + | Iir_Value_Environment => raise Internal_Error; end case; end Create_Signal; |