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| author | Tristan Gingold | 2015-01-13 20:19:26 +0100 |
|---|---|---|
| committer | Tristan Gingold | 2015-01-13 20:19:26 +0100 |
| commit | d5a8c6796715ec5effeb620ec660f996cf2446f9 (patch) | |
| tree | 91766e79312d02e8810d4b5b92b33e80b93ccc22 /src/ortho/mcode | |
| parent | f6227b6be67383fd0e6d8fd6c273509515ac3bc0 (diff) | |
| download | ghdl-d5a8c6796715ec5effeb620ec660f996cf2446f9.tar.gz ghdl-d5a8c6796715ec5effeb620ec660f996cf2446f9.tar.bz2 ghdl-d5a8c6796715ec5effeb620ec660f996cf2446f9.zip | |
mcode: fix ticket#32 - spill the right instruction.
Diffstat (limited to 'src/ortho/mcode')
| -rw-r--r-- | src/ortho/mcode/ortho_code-x86-insns.adb | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/src/ortho/mcode/ortho_code-x86-insns.adb b/src/ortho/mcode/ortho_code-x86-insns.adb index e600f47..2a04e93 100644 --- a/src/ortho/mcode/ortho_code-x86-insns.adb +++ b/src/ortho/mcode/ortho_code-x86-insns.adb @@ -486,6 +486,7 @@ package body Ortho_Code.X86.Insns is end if; Free_R32 (Reg); when Regs_R64 => + -- The pair was spilled, so the pair is free. Free_R32 (Get_R64_High (Reg_Orig)); Free_R32 (Get_R64_Low (Reg_Orig)); when others => @@ -1090,10 +1091,11 @@ package body Ortho_Code.X86.Insns is function Gen_Insn (Stmt : O_Enode; Reg : O_Reg; Pnum : O_Inum) return O_Enode is - Kind : OE_Kind; + Kind : constant OE_Kind := Get_Expr_Kind (Stmt); Left : O_Enode; Right : O_Enode; + Res : O_Enode; Reg1 : O_Reg; -- P_Reg : O_Reg; @@ -1102,7 +1104,6 @@ package body Ortho_Code.X86.Insns is Num : O_Inum; begin - Kind := Get_Expr_Kind (Stmt); case Kind is when OE_Addrl => Right := Get_Addrl_Frame (Stmt); @@ -1382,13 +1383,17 @@ package body Ortho_Code.X86.Insns is return Stmt; when R_Any8 | Regs_R8 => - Reg_Res := Alloc_Reg (Reg, Stmt, Pnum); - return Insert_Move (Stmt, Reg_Res); + Res := Insert_Move (Stmt, R_Any8); + Reg_Res := Alloc_Reg (Reg, Res, Pnum); + Set_Expr_Reg (Res, Reg_Res); + return Res; when R_Irm | R_Ir | R_Rm => - Reg_Res := Alloc_Reg (R_Any8, Stmt, Pnum); - return Insert_Move (Stmt, Reg_Res); + Res := Insert_Move (Stmt, R_Any32); + Reg_Res := Alloc_Reg (R_Any8, Res, Pnum); + Set_Expr_Reg (Res, Reg_Res); + return Res; when others => Error_Gen_Insn (Stmt, Reg); end case; |