blob: 1b07f6fd6391d00c4e05934baa793f79e3864b35 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
|
* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\375\375.cir
* u2 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ d_dlatch
* u3 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ d_dlatch
* u4 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ d_dlatch
* u5 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ d_dlatch
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port
a1 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ u2
a2 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ u3
a3 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ u4
a4 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ u5
* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
.tran 0e-00 0e-00 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
|
