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* Subcircuit 74ls47
.subckt 74ls47 /w /x /y /z net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ?
* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls47\74ls47.cir
.include 3_and.sub
.include g_origin.sub
.include e_origin.sub
.include a_origin.sub
.include 4_OR.sub
.include c_origin.sub
.include d_origin.sub
.include b_origin.sub
.include f_origin.sub
x3 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u5-pad1_ a_origin
x5 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u7-pad1_ c_origin
x6 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u8-pad1_ d_origin
x7 net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u11-pad1_ e_origin
x8 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u9-pad1_ f_origin
* u3 /w /x /y /z net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
x1 /rbi net-_u3-pad8_ net-_u3-pad7_ net-_u3-pad6_ net-_u4-pad1_ 4_OR
* u4 net-_u4-pad1_ net-_u3-pad5_ net-_u4-pad3_ d_or
x2 /lt /bi net-_u4-pad3_ net-_u10-pad2_ 3_and
* u5 net-_u5-pad1_ net-_u10-pad2_ net-_u12-pad1_ d_and
* u6 net-_u6-pad1_ net-_u10-pad2_ net-_u12-pad2_ d_and
* u7 net-_u7-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_and
* u8 net-_u8-pad1_ net-_u10-pad2_ net-_u12-pad4_ d_and
* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and
* u9 net-_u9-pad1_ net-_u10-pad2_ net-_u12-pad6_ d_and
* u2 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ /lt /bi /rbi adc_bridge_3
* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_7
* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
x4 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u6-pad1_ b_origin
x9 net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u10-pad1_ g_origin
a1 [/w /x /y /z ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
a2 [net-_u4-pad1_ net-_u3-pad5_ ] net-_u4-pad3_ u4
a3 [net-_u5-pad1_ net-_u10-pad2_ ] net-_u12-pad1_ u5
a4 [net-_u6-pad1_ net-_u10-pad2_ ] net-_u12-pad2_ u6
a5 [net-_u7-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u7
a6 [net-_u8-pad1_ net-_u10-pad2_ ] net-_u12-pad4_ u8
a7 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
a8 [net-_u9-pad1_ net-_u10-pad2_ ] net-_u12-pad6_ u9
a9 [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] [/lt /bi /rbi ] u2
a10 [net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ net-_u12-pad4_ net-_u11-pad3_ net-_u12-pad6_ net-_u10-pad3_ ] [net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u12
a11 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: dac_bridge_7, NgSpice Name: dac_bridge
.model u12 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements
.ends 74ls47
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