blob: 1442a155fa501691f119a3125deec1a1eb1b0a63 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
* Subcircuit mux4
.subckt mux4 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
* c:\fossee\esim\library\subcircuitlibrary\mux4\mux4.cir
.include 3_and.sub
.include 4_OR.sub
* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
x1 net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad6_ net-_x1-pad4_ 3_and
x2 net-_u1-pad1_ net-_u3-pad2_ net-_u1-pad3_ net-_x2-pad4_ 3_and
x3 net-_u2-pad2_ net-_u1-pad2_ net-_u1-pad4_ net-_x3-pad4_ 3_and
x4 net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ net-_x4-pad4_ 3_and
x5 net-_x1-pad4_ net-_x2-pad4_ net-_x3-pad4_ net-_x4-pad4_ net-_u1-pad7_ 4_OR
a1 net-_u1-pad1_ net-_u2-pad2_ u2
a2 net-_u1-pad2_ net-_u3-pad2_ u3
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements
.ends mux4
|
