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* Subcircuit Sn75160b
.subckt Sn75160b net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ gnd gnd
* c:\fossee\esim\library\subcircuitlibrary\sn75160b\sn75160b.cir
* u8 net-_u1-pad8_ /te net-_u1-pad3_ tristate_buffer_active_low
* u4 net-_u1-pad3_ /pe ? net-_u1-pad8_ buffer_4pin
* u2 net-_u1-pad1_ /pe d_buffer
* u3 net-_u1-pad2_ /te d_buffer
* u9 net-_u1-pad7_ /te net-_u1-pad4_ tristate_buffer_active_low
* u5 net-_u1-pad4_ /pe ? net-_u1-pad7_ buffer_4pin
* u10 net-_u1-pad9_ /te net-_u1-pad5_ tristate_buffer_active_low
* u6 net-_u1-pad5_ /pe ? net-_u1-pad9_ buffer_4pin
* u11 net-_u1-pad10_ /te net-_u1-pad6_ tristate_buffer_active_low
* u7 net-_u1-pad6_ /pe ? net-_u1-pad10_ buffer_4pin
* u16 net-_u1-pad16_ /te net-_u1-pad11_ tristate_buffer_active_low
* u12 net-_u1-pad11_ /pe ? net-_u1-pad16_ buffer_4pin
* u17 net-_u1-pad15_ /te net-_u1-pad12_ tristate_buffer_active_low
* u13 net-_u1-pad12_ /pe ? net-_u1-pad15_ buffer_4pin
* u18 net-_u1-pad17_ /te net-_u1-pad13_ tristate_buffer_active_low
* u14 net-_u1-pad13_ /pe ? net-_u1-pad17_ buffer_4pin
* u19 net-_u1-pad18_ /te net-_u1-pad14_ tristate_buffer_active_low
* u15 net-_u1-pad14_ /pe ? net-_u1-pad18_ buffer_4pin
a1 [net-_u1-pad8_ ] [/te ] [net-_u1-pad3_ ] u8
a2 [net-_u1-pad3_ ] [/pe ] [? ] [net-_u1-pad8_ ] u4
a3 net-_u1-pad1_ /pe u2
a4 net-_u1-pad2_ /te u3
a5 [net-_u1-pad7_ ] [/te ] [net-_u1-pad4_ ] u9
a6 [net-_u1-pad4_ ] [/pe ] [? ] [net-_u1-pad7_ ] u5
a7 [net-_u1-pad9_ ] [/te ] [net-_u1-pad5_ ] u10
a8 [net-_u1-pad5_ ] [/pe ] [? ] [net-_u1-pad9_ ] u6
a9 [net-_u1-pad10_ ] [/te ] [net-_u1-pad6_ ] u11
a10 [net-_u1-pad6_ ] [/pe ] [? ] [net-_u1-pad10_ ] u7
a11 [net-_u1-pad16_ ] [/te ] [net-_u1-pad11_ ] u16
a12 [net-_u1-pad11_ ] [/pe ] [? ] [net-_u1-pad16_ ] u12
a13 [net-_u1-pad15_ ] [/te ] [net-_u1-pad12_ ] u17
a14 [net-_u1-pad12_ ] [/pe ] [? ] [net-_u1-pad15_ ] u13
a15 [net-_u1-pad17_ ] [/te ] [net-_u1-pad13_ ] u18
a16 [net-_u1-pad13_ ] [/pe ] [? ] [net-_u1-pad17_ ] u14
a17 [net-_u1-pad18_ ] [/te ] [net-_u1-pad14_ ] u19
a18 [net-_u1-pad14_ ] [/pe ] [? ] [net-_u1-pad18_ ] u15
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u8 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u4 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u9 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u5 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u10 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u6 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u11 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u7 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u16 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u12 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u17 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u13 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u18 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u14 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: tristate_buffer_active_low, NgSpice Name: tristate_buffer_active_low
.model u19 tristate_buffer_active_low(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Schematic Name: buffer_4pin, NgSpice Name: buffer_4pin
.model u15 buffer_4pin(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
* Control Statements
.ends Sn75160b
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