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* c:\users\public\music\fossee\esim\library\subcircuitlibrary\sn54f521\sn54f521.cir
.include 4_and.sub
x2 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u23-pad3_ net-_u28-pad1_ 4_and
x1 net-_u22-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u28-pad2_ 4_and
* u2 net-_u1-pad17_ net-_u19-pad1_ d_inverter
* u3 net-_u1-pad18_ net-_u19-pad2_ d_inverter
* u4 net-_u1-pad15_ net-_u20-pad1_ d_inverter
* u5 net-_u1-pad16_ net-_u20-pad2_ d_inverter
* u6 net-_u1-pad13_ net-_u21-pad1_ d_inverter
* u7 net-_u1-pad14_ net-_u21-pad2_ d_inverter
* u10 net-_u1-pad11_ net-_u10-pad2_ d_inverter
* u11 net-_u1-pad12_ net-_u11-pad2_ d_inverter
* u8 net-_u1-pad8_ net-_u22-pad1_ d_inverter
* u9 net-_u1-pad9_ net-_u22-pad2_ d_inverter
* u12 net-_u1-pad6_ net-_u12-pad2_ d_inverter
* u13 net-_u1-pad7_ net-_u13-pad2_ d_inverter
* u14 net-_u1-pad4_ net-_u14-pad2_ d_inverter
* u15 net-_u1-pad5_ net-_u15-pad2_ d_inverter
* u16 net-_u1-pad2_ net-_u16-pad2_ d_inverter
* u17 net-_u1-pad3_ net-_u17-pad2_ d_inverter
* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
* u27 net-_u18-pad2_ net-_u27-pad2_ d_buffer
* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and
* u30 net-_u29-pad3_ net-_u1-pad19_ d_inverter
* u29 net-_u28-pad3_ net-_u27-pad2_ net-_u29-pad3_ d_and
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port
* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_xnor
* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_xnor
* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_xnor
* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_xnor
* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_xnor
* u25 net-_u14-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_xnor
* u26 net-_u16-pad2_ net-_u17-pad2_ net-_u26-pad3_ d_xnor
a1 net-_u1-pad17_ net-_u19-pad1_ u2
a2 net-_u1-pad18_ net-_u19-pad2_ u3
a3 net-_u1-pad15_ net-_u20-pad1_ u4
a4 net-_u1-pad16_ net-_u20-pad2_ u5
a5 net-_u1-pad13_ net-_u21-pad1_ u6
a6 net-_u1-pad14_ net-_u21-pad2_ u7
a7 net-_u1-pad11_ net-_u10-pad2_ u10
a8 net-_u1-pad12_ net-_u11-pad2_ u11
a9 net-_u1-pad8_ net-_u22-pad1_ u8
a10 net-_u1-pad9_ net-_u22-pad2_ u9
a11 net-_u1-pad6_ net-_u12-pad2_ u12
a12 net-_u1-pad7_ net-_u13-pad2_ u13
a13 net-_u1-pad4_ net-_u14-pad2_ u14
a14 net-_u1-pad5_ net-_u15-pad2_ u15
a15 net-_u1-pad2_ net-_u16-pad2_ u16
a16 net-_u1-pad3_ net-_u17-pad2_ u17
a17 net-_u1-pad1_ net-_u18-pad2_ u18
a18 net-_u18-pad2_ net-_u27-pad2_ u27
a19 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
a20 net-_u29-pad3_ net-_u1-pad19_ u30
a21 [net-_u28-pad3_ net-_u27-pad2_ ] net-_u29-pad3_ u29
a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
a23 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
a24 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
a26 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
a27 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
a28 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
a29 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u26-pad3_ u26
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
.tran 0e-00 0e-00 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
|
