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* c:\fossee\esim\library\subcircuitlibrary\mc74hc238\mc74hc238.cir
.include 3_and.sub
* u37 net-_u21-pad2_ net-_u22-pad2_ net-_u1-pad7_ d_and
* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter
* u22 net-_u17-pad3_ net-_u22-pad2_ d_inverter
* u38 net-_u23-pad2_ net-_u24-pad2_ net-_u1-pad8_ d_and
* u23 net-_u19-pad2_ net-_u23-pad2_ d_inverter
* u24 net-_u17-pad3_ net-_u24-pad2_ d_inverter
* u39 net-_u25-pad2_ net-_u26-pad2_ net-_u1-pad9_ d_and
* u25 net-_u20-pad2_ net-_u25-pad2_ d_inverter
* u26 net-_u17-pad3_ net-_u26-pad2_ d_inverter
* u40 net-_u27-pad2_ net-_u28-pad2_ net-_u1-pad10_ d_and
* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter
* u28 net-_u17-pad3_ net-_u28-pad2_ d_inverter
* u41 net-_u29-pad2_ net-_u30-pad2_ net-_u1-pad11_ d_and
* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter
* u30 net-_u17-pad3_ net-_u30-pad2_ d_inverter
* u42 net-_u31-pad2_ net-_u32-pad2_ net-_u1-pad12_ d_and
* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter
* u32 net-_u17-pad3_ net-_u32-pad2_ d_inverter
* u43 net-_u33-pad2_ net-_u34-pad2_ net-_u1-pad13_ d_and
* u33 net-_u33-pad1_ net-_u33-pad2_ d_inverter
* u34 net-_u17-pad3_ net-_u34-pad2_ d_inverter
* u44 net-_u35-pad2_ net-_u36-pad2_ net-_u1-pad14_ d_and
* u35 net-_u35-pad1_ net-_u35-pad2_ d_inverter
* u36 net-_u17-pad3_ net-_u36-pad2_ d_inverter
* u10 net-_u1-pad1_ net-_u10-pad2_ d_inverter
* u11 net-_u1-pad2_ net-_u11-pad2_ d_inverter
* u12 net-_u1-pad3_ net-_u12-pad2_ d_inverter
* u14 net-_u10-pad2_ net-_u14-pad2_ d_inverter
* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter
* u16 net-_u12-pad2_ net-_u16-pad2_ d_inverter
* u17 net-_u13-pad3_ net-_u1-pad6_ net-_u17-pad3_ d_nand
* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_and
* u8 net-_u1-pad4_ net-_u13-pad1_ d_inverter
* u9 net-_u1-pad5_ net-_u13-pad2_ d_inverter
x1 net-_u10-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u18-pad1_ 3_and
x2 net-_u14-pad2_ net-_u11-pad2_ net-_u12-pad2_ net-_u19-pad1_ 3_and
x3 net-_u10-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u20-pad1_ 3_and
x4 net-_u14-pad2_ net-_u15-pad2_ net-_u12-pad2_ net-_u54-pad1_ 3_and
x5 net-_u10-pad2_ net-_u11-pad2_ net-_u16-pad2_ net-_u55-pad1_ 3_and
x6 net-_u11-pad2_ net-_u16-pad2_ net-_u10-pad2_ net-_u56-pad1_ 3_and
x8 net-_u14-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u58-pad1_ 3_and
x7 net-_u10-pad2_ net-_u15-pad2_ net-_u16-pad2_ net-_u57-pad1_ 3_and
* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
* u54 net-_u54-pad1_ net-_u27-pad1_ d_inverter
* u55 net-_u55-pad1_ net-_u29-pad1_ d_inverter
* u56 net-_u56-pad1_ net-_u31-pad1_ d_inverter
* u57 net-_u57-pad1_ net-_u33-pad1_ d_inverter
* u58 net-_u58-pad1_ net-_u35-pad1_ d_inverter
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
a1 [net-_u21-pad2_ net-_u22-pad2_ ] net-_u1-pad7_ u37
a2 net-_u18-pad2_ net-_u21-pad2_ u21
a3 net-_u17-pad3_ net-_u22-pad2_ u22
a4 [net-_u23-pad2_ net-_u24-pad2_ ] net-_u1-pad8_ u38
a5 net-_u19-pad2_ net-_u23-pad2_ u23
a6 net-_u17-pad3_ net-_u24-pad2_ u24
a7 [net-_u25-pad2_ net-_u26-pad2_ ] net-_u1-pad9_ u39
a8 net-_u20-pad2_ net-_u25-pad2_ u25
a9 net-_u17-pad3_ net-_u26-pad2_ u26
a10 [net-_u27-pad2_ net-_u28-pad2_ ] net-_u1-pad10_ u40
a11 net-_u27-pad1_ net-_u27-pad2_ u27
a12 net-_u17-pad3_ net-_u28-pad2_ u28
a13 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u1-pad11_ u41
a14 net-_u29-pad1_ net-_u29-pad2_ u29
a15 net-_u17-pad3_ net-_u30-pad2_ u30
a16 [net-_u31-pad2_ net-_u32-pad2_ ] net-_u1-pad12_ u42
a17 net-_u31-pad1_ net-_u31-pad2_ u31
a18 net-_u17-pad3_ net-_u32-pad2_ u32
a19 [net-_u33-pad2_ net-_u34-pad2_ ] net-_u1-pad13_ u43
a20 net-_u33-pad1_ net-_u33-pad2_ u33
a21 net-_u17-pad3_ net-_u34-pad2_ u34
a22 [net-_u35-pad2_ net-_u36-pad2_ ] net-_u1-pad14_ u44
a23 net-_u35-pad1_ net-_u35-pad2_ u35
a24 net-_u17-pad3_ net-_u36-pad2_ u36
a25 net-_u1-pad1_ net-_u10-pad2_ u10
a26 net-_u1-pad2_ net-_u11-pad2_ u11
a27 net-_u1-pad3_ net-_u12-pad2_ u12
a28 net-_u10-pad2_ net-_u14-pad2_ u14
a29 net-_u11-pad2_ net-_u15-pad2_ u15
a30 net-_u12-pad2_ net-_u16-pad2_ u16
a31 [net-_u13-pad3_ net-_u1-pad6_ ] net-_u17-pad3_ u17
a32 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
a33 net-_u1-pad4_ net-_u13-pad1_ u8
a34 net-_u1-pad5_ net-_u13-pad2_ u9
a35 net-_u18-pad1_ net-_u18-pad2_ u18
a36 net-_u19-pad1_ net-_u19-pad2_ u19
a37 net-_u20-pad1_ net-_u20-pad2_ u20
a38 net-_u54-pad1_ net-_u27-pad1_ u54
a39 net-_u55-pad1_ net-_u29-pad1_ u55
a40 net-_u56-pad1_ net-_u31-pad1_ u56
a41 net-_u57-pad1_ net-_u33-pad1_ u57
a42 net-_u58-pad1_ net-_u35-pad1_ u58
* Schematic Name: d_and, NgSpice Name: d_and
.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, NgSpice Name: d_nand
.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u57 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u58 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
.tran 0e-03 0e-00 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
|
