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* Subcircuit MC10H166
.subckt MC10H166 ? net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
* c:\users\public\music\fossee\esim\library\subcircuitlibrary\mc10h166\mc10h166.cir
.include 4_OR.sub
* u10 net-_u1-pad13_ net-_u1-pad14_ net-_u10-pad3_ d_xor
* u9 net-_u1-pad14_ net-_u3-pad2_ net-_u19-pad2_ d_or
* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter
* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_nor
x3 net-_u17-pad1_ net-_u13-pad3_ net-_u14-pad3_ net-_u10-pad3_ net-_u21-pad1_ 4_OR
x2 net-_u12-pad3_ net-_u14-pad3_ net-_u17-pad1_ net-_u10-pad3_ net-_u24-pad1_ 4_OR
* u24 net-_u24-pad1_ net-_u16-pad3_ net-_u24-pad3_ d_or
* u26 net-_u24-pad3_ net-_u26-pad2_ d_inverter
x1 net-_u17-pad1_ net-_u14-pad3_ net-_u10-pad3_ net-_u16-pad3_ net-_u22-pad1_ 4_OR
* u22 net-_u22-pad1_ net-_u11-pad3_ net-_u22-pad3_ d_or
* u25 net-_u22-pad3_ net-_u25-pad2_ d_inverter
* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
* u17 net-_u17-pad1_ net-_u15-pad3_ net-_u17-pad3_ d_or
* u20 net-_u17-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
* u23 net-_u20-pad3_ net-_u23-pad2_ d_inverter
x4 net-_u18-pad2_ net-_u21-pad2_ net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad1_ 4_OR
* u27 net-_u27-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_or
* u28 net-_u26-pad2_ net-_u1-pad15_ net-_u28-pad3_ d_or
* u31 net-_u28-pad3_ net-_u27-pad3_ net-_u31-pad3_ d_or
* u32 net-_u31-pad3_ net-_u1-pad2_ d_inverter
* u30 net-_u27-pad3_ net-_u29-pad2_ net-_u1-pad3_ d_and
* u29 net-_u1-pad15_ net-_u29-pad2_ d_inverter
* u14 net-_u1-pad12_ net-_u1-pad11_ net-_u14-pad3_ d_xor
* u13 net-_u1-pad11_ net-_u13-pad2_ net-_u13-pad3_ d_or
* u5 net-_u1-pad12_ net-_u13-pad2_ d_inverter
* u12 net-_u1-pad5_ net-_u1-pad4_ net-_u12-pad3_ d_xor
* u11 net-_u1-pad4_ net-_u11-pad2_ net-_u11-pad3_ d_or
* u4 net-_u1-pad5_ net-_u11-pad2_ d_inverter
* u16 net-_u1-pad6_ net-_u1-pad7_ net-_u16-pad3_ d_xor
* u15 net-_u1-pad7_ net-_u15-pad2_ net-_u15-pad3_ d_or
* u6 net-_u1-pad6_ net-_u15-pad2_ d_inverter
* u8 net-_u1-pad9_ net-_u1-pad10_ net-_u17-pad1_ d_xor
* u7 net-_u1-pad10_ net-_u2-pad2_ net-_u18-pad1_ d_or
* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
a1 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u10-pad3_ u10
a2 [net-_u1-pad14_ net-_u3-pad2_ ] net-_u19-pad2_ u9
a3 net-_u1-pad13_ net-_u3-pad2_ u3
a4 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
a5 [net-_u24-pad1_ net-_u16-pad3_ ] net-_u24-pad3_ u24
a6 net-_u24-pad3_ net-_u26-pad2_ u26
a7 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u22-pad3_ u22
a8 net-_u22-pad3_ net-_u25-pad2_ u25
a9 net-_u21-pad1_ net-_u21-pad2_ u21
a10 net-_u18-pad1_ net-_u18-pad2_ u18
a11 [net-_u17-pad1_ net-_u15-pad3_ ] net-_u17-pad3_ u17
a12 [net-_u17-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
a13 net-_u20-pad3_ net-_u23-pad2_ u23
a14 [net-_u27-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27
a15 [net-_u26-pad2_ net-_u1-pad15_ ] net-_u28-pad3_ u28
a16 [net-_u28-pad3_ net-_u27-pad3_ ] net-_u31-pad3_ u31
a17 net-_u31-pad3_ net-_u1-pad2_ u32
a18 [net-_u27-pad3_ net-_u29-pad2_ ] net-_u1-pad3_ u30
a19 net-_u1-pad15_ net-_u29-pad2_ u29
a20 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u14-pad3_ u14
a21 [net-_u1-pad11_ net-_u13-pad2_ ] net-_u13-pad3_ u13
a22 net-_u1-pad12_ net-_u13-pad2_ u5
a23 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u12-pad3_ u12
a24 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u11-pad3_ u11
a25 net-_u1-pad5_ net-_u11-pad2_ u4
a26 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u16-pad3_ u16
a27 [net-_u1-pad7_ net-_u15-pad2_ ] net-_u15-pad3_ u15
a28 net-_u1-pad6_ net-_u15-pad2_ u6
a29 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u17-pad1_ u8
a30 [net-_u1-pad10_ net-_u2-pad2_ ] net-_u18-pad1_ u7
a31 net-_u1-pad9_ net-_u2-pad2_ u2
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nor, NgSpice Name: d_nor
.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u16 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xor, NgSpice Name: d_xor
.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_or, NgSpice Name: d_or
.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements
.ends MC10H166
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