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* Subcircuit DM74LS460
.subckt DM74LS460 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ?
* c:\users\public\music\fossee\esim\library\subcircuitlibrary\dm74ls460\dm74ls460.cir
.include 4_and.sub
.include 3_and.sub
* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_xnor
* u3 net-_u1-pad22_ net-_u1-pad23_ net-_u3-pad3_ d_xnor
* u8 net-_u1-pad1_ net-_u1-pad2_ net-_u8-pad3_ d_xnor
* u9 net-_u1-pad3_ net-_u1-pad4_ net-_u9-pad3_ d_xnor
* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_xnor
* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_xnor
* u10 net-_u1-pad9_ net-_u1-pad10_ net-_u10-pad3_ d_xnor
* u11 net-_u1-pad11_ net-_u1-pad13_ net-_u11-pad3_ d_xnor
* u6 net-_u1-pad14_ net-_u1-pad15_ net-_u12-pad1_ d_xnor
* u7 net-_u1-pad16_ net-_u1-pad17_ net-_u12-pad2_ d_xnor
x1 net-_u2-pad3_ net-_u3-pad3_ net-_u8-pad3_ net-_u9-pad3_ net-_x1-pad5_ 4_and
x2 net-_u4-pad3_ net-_u5-pad3_ net-_u10-pad3_ net-_u11-pad3_ net-_x2-pad5_ 4_and
* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
x3 net-_x1-pad5_ net-_x2-pad5_ net-_u12-pad3_ net-_u13-pad1_ 3_and
* u14 net-_u13-pad1_ net-_u1-pad18_ d_buffer
* u13 net-_u13-pad1_ net-_u1-pad19_ d_inverter
a1 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2
a2 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u3-pad3_ u3
a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u8-pad3_ u8
a4 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u9-pad3_ u9
a5 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4
a6 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5
a7 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u10-pad3_ u10
a8 [net-_u1-pad11_ net-_u1-pad13_ ] net-_u11-pad3_ u11
a9 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u12-pad1_ u6
a10 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u12-pad2_ u7
a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
a12 net-_u13-pad1_ net-_u1-pad18_ u14
a13 net-_u13-pad1_ net-_u1-pad19_ u13
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u2 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u11 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_xnor, NgSpice Name: d_xnor
.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_buffer, NgSpice Name: d_buffer
.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements
.ends DM74LS460
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