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* c:\fossee\esim\library\subcircuitlibrary\serial_d_4\serial_d_4.cir
* u3 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u3-pad5_ ? d_dff
* u5 net-_u4-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u5-pad5_ ? d_dff
* u6 net-_u5-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u1-pad4_ ? d_dff
* u7 net-_u3-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad1_ ? d_dff
* u8 net-_u4-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u14-pad1_ ? d_dff
* u9 net-_u5-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ ? d_dff
* u10 net-_u1-pad4_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad5_ ? d_dff
* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u1-pad7_ d_tristate
* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u1-pad8_ d_tristate
* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad5_ d_tristate
* u12 net-_u10-pad5_ net-_u11-pad2_ net-_u1-pad6_ d_tristate
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port
* u15 net-_u1-pad10_ net-_u11-pad2_ d_inverter
* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
* u4 net-_u3-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u4-pad5_ ? d_dff
a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u3-pad5_ ? u3
a2 net-_u4-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u5-pad5_ ? u5
a3 net-_u5-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u1-pad4_ ? u6
a4 net-_u3-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u13-pad1_ ? u7
a5 net-_u4-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u14-pad1_ ? u8
a6 net-_u5-pad5_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u11-pad1_ ? u9
a7 net-_u1-pad4_ net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad11_ net-_u10-pad5_ ? u10
a8 net-_u13-pad1_ net-_u11-pad2_ net-_u1-pad7_ u13
a9 net-_u14-pad1_ net-_u11-pad2_ net-_u1-pad8_ u14
a10 net-_u11-pad1_ net-_u11-pad2_ net-_u1-pad5_ u11
a11 net-_u10-pad5_ net-_u11-pad2_ net-_u1-pad6_ u12
a12 net-_u1-pad10_ net-_u11-pad2_ u15
a13 net-_u1-pad2_ net-_u2-pad2_ u2
a14 net-_u3-pad5_ net-_u1-pad1_ net-_u1-pad11_ net-_u2-pad2_ net-_u4-pad5_ ? u4
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u13 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_tristate, NgSpice Name: d_tristate
.model u12 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
.tran 0e-00 0e-00 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
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