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* Subcircuit 74HC175
.subckt 74HC175 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
* c:\fossee\esim\library\subcircuitlibrary\74hc175\74hc175.cir
* u2 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_dff
* u3 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ d_dff
* u4 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ d_dff
* u5 net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ d_dff
* u6 net-_u1-pad2_ net-_u2-pad4_ d_inverter
a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ u2
a2 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ u3
a3 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ u4
a4 net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ u5
a5 net-_u1-pad2_ net-_u2-pad4_ u6
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u2 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_dff, NgSpice Name: d_dff
.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
* Schematic Name: d_inverter, NgSpice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Control Statements
.ends 74HC175
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