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* c:\fossee\esim\library\subcircuitlibrary\743253\743253.cir
.include PMOS-180nm.lib
.include NMOS-180nm.lib
m18 b11 net-_m10-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m10 net-_m10-pad1_ c1 gnd gnd CMOSN W=100u L=100u M=1
m11 net-_m10-pad1_ c1 vdd vdd CMOSP W=100u L=100u M=1
m17 a1 c1 b11 b11 CMOSN W=100u L=100u M=1
m12 net-_m12-pad1_ sb0 net-_m12-pad3_ net-_m12-pad3_ CMOSN W=100u L=100u M=1
m13 net-_m12-pad3_ sb1 net-_m13-pad3_ net-_m13-pad3_ CMOSN W=100u L=100u M=1
m14 net-_m13-pad3_ e1 gnd gnd CMOSN W=100u L=100u M=1
m15 net-_m12-pad1_ sb1 vdd vdd CMOSP W=100u L=100u M=1
m16 net-_m12-pad1_ e1 vdd vdd CMOSP W=100u L=100u M=1
m9 net-_m12-pad1_ sb0 vdd vdd CMOSP W=100u L=100u M=1
m20 c1 net-_m12-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m19 c1 net-_m12-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m1 sb0 s0 gnd gnd CMOSN W=100u L=100u M=1
m5 sb0 s0 vdd vdd CMOSP W=100u L=100u M=1
m2 sb1 s1 gnd gnd CMOSN W=100u L=100u M=1
m6 sb1 s1 vdd vdd CMOSP W=100u L=100u M=1
m3 e1 oe1 gnd gnd CMOSN W=100u L=100u M=1
m7 e1 oe1 vdd vdd CMOSP W=100u L=100u M=1
m30 b12 net-_m22-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m22 net-_m22-pad1_ c2 gnd gnd CMOSN W=100u L=100u M=1
m23 net-_m22-pad1_ c2 vdd vdd CMOSP W=100u L=100u M=1
m29 a1 c2 b12 b12 CMOSN W=100u L=100u M=1
m24 net-_m21-pad1_ s0 net-_m24-pad3_ net-_m24-pad3_ CMOSN W=100u L=100u M=1
m25 net-_m24-pad3_ sb1 net-_m25-pad3_ net-_m25-pad3_ CMOSN W=100u L=100u M=1
m26 net-_m25-pad3_ e1 gnd gnd CMOSN W=100u L=100u M=1
m27 net-_m21-pad1_ sb1 vdd vdd CMOSP W=100u L=100u M=1
m28 net-_m21-pad1_ e1 vdd vdd CMOSP W=100u L=100u M=1
m21 net-_m21-pad1_ s0 vdd vdd CMOSP W=100u L=100u M=1
m32 c2 net-_m21-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m31 c2 net-_m21-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m42 b13 net-_m34-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m34 net-_m34-pad1_ c3 gnd gnd CMOSN W=100u L=100u M=1
m35 net-_m34-pad1_ c3 vdd vdd CMOSP W=100u L=100u M=1
m41 a1 c3 b13 b13 CMOSN W=100u L=100u M=1
m36 net-_m33-pad1_ sb0 net-_m36-pad3_ net-_m36-pad3_ CMOSN W=100u L=100u M=1
m37 net-_m36-pad3_ s1 net-_m37-pad3_ net-_m37-pad3_ CMOSN W=100u L=100u M=1
m38 net-_m37-pad3_ e1 gnd gnd CMOSN W=100u L=100u M=1
m39 net-_m33-pad1_ s1 vdd vdd CMOSP W=100u L=100u M=1
m40 net-_m33-pad1_ e1 vdd vdd CMOSP W=100u L=100u M=1
m33 net-_m33-pad1_ sb0 vdd vdd CMOSP W=100u L=100u M=1
m44 c3 net-_m33-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m43 c3 net-_m33-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m54 b14 net-_m46-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m46 net-_m46-pad1_ c4 gnd gnd CMOSN W=100u L=100u M=1
m47 net-_m46-pad1_ c4 vdd vdd CMOSP W=100u L=100u M=1
m53 a1 c4 b14 b14 CMOSN W=100u L=100u M=1
m48 net-_m45-pad1_ s0 net-_m48-pad3_ net-_m48-pad3_ CMOSN W=100u L=100u M=1
m49 net-_m48-pad3_ s1 net-_m49-pad3_ net-_m49-pad3_ CMOSN W=100u L=100u M=1
m50 net-_m49-pad3_ e1 gnd gnd CMOSN W=100u L=100u M=1
m51 net-_m45-pad1_ s1 vdd vdd CMOSP W=100u L=100u M=1
m52 net-_m45-pad1_ e1 vdd vdd CMOSP W=100u L=100u M=1
m45 net-_m45-pad1_ s0 vdd vdd CMOSP W=100u L=100u M=1
m56 c4 net-_m45-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m55 c4 net-_m45-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m4 e2 oe2 gnd gnd CMOSN W=100u L=100u M=1
m8 e2 oe2 vdd vdd CMOSP W=100u L=100u M=1
m66 b21 net-_m58-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m58 net-_m58-pad1_ c5 gnd gnd CMOSN W=100u L=100u M=1
m59 net-_m58-pad1_ c5 vdd vdd CMOSP W=100u L=100u M=1
m65 a1 c5 b21 b21 CMOSN W=100u L=100u M=1
m60 net-_m57-pad1_ sb0 net-_m60-pad3_ net-_m60-pad3_ CMOSN W=100u L=100u M=1
m61 net-_m60-pad3_ sb1 net-_m61-pad3_ net-_m61-pad3_ CMOSN W=100u L=100u M=1
m62 net-_m61-pad3_ e2 gnd gnd CMOSN W=100u L=100u M=1
m63 net-_m57-pad1_ sb1 vdd vdd CMOSP W=100u L=100u M=1
m64 net-_m57-pad1_ e2 vdd vdd CMOSP W=100u L=100u M=1
m57 net-_m57-pad1_ sb0 vdd vdd CMOSP W=100u L=100u M=1
m68 c5 net-_m57-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m67 c5 net-_m57-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m78 b22 net-_m70-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m70 net-_m70-pad1_ c6 gnd gnd CMOSN W=100u L=100u M=1
m71 net-_m70-pad1_ c6 vdd vdd CMOSP W=100u L=100u M=1
m77 a1 c6 b22 b22 CMOSN W=100u L=100u M=1
m72 net-_m69-pad1_ s0 net-_m72-pad3_ net-_m72-pad3_ CMOSN W=100u L=100u M=1
m73 net-_m72-pad3_ sb1 net-_m73-pad3_ net-_m73-pad3_ CMOSN W=100u L=100u M=1
m74 net-_m73-pad3_ e2 gnd gnd CMOSN W=100u L=100u M=1
m75 net-_m69-pad1_ sb1 vdd vdd CMOSP W=100u L=100u M=1
m76 net-_m69-pad1_ e2 vdd vdd CMOSP W=100u L=100u M=1
m69 net-_m69-pad1_ s0 vdd vdd CMOSP W=100u L=100u M=1
m80 c6 net-_m69-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m79 c6 net-_m69-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m90 b23 net-_m82-pad1_ a1 a1 CMOSP W=100u L=100u M=1
m82 net-_m82-pad1_ c7 gnd gnd CMOSN W=100u L=100u M=1
m83 net-_m82-pad1_ c7 vdd vdd CMOSP W=100u L=100u M=1
m89 a1 c7 b23 b23 CMOSN W=100u L=100u M=1
m84 net-_m81-pad1_ sb0 net-_m84-pad3_ net-_m84-pad3_ CMOSN W=100u L=100u M=1
m85 net-_m84-pad3_ s1 net-_m85-pad3_ net-_m85-pad3_ CMOSN W=100u L=100u M=1
m86 net-_m85-pad3_ e2 gnd gnd CMOSN W=100u L=100u M=1
m87 net-_m81-pad1_ s1 vdd vdd CMOSP W=100u L=100u M=1
m88 net-_m81-pad1_ e2 vdd vdd CMOSP W=100u L=100u M=1
m81 net-_m81-pad1_ sb0 vdd vdd CMOSP W=100u L=100u M=1
m92 c7 net-_m81-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m91 c7 net-_m81-pad1_ gnd gnd CMOSN W=100u L=100u M=1
m102 b24 net-_m102-pad2_ a1 a1 CMOSP W=100u L=100u M=1
m94 net-_m102-pad2_ c8 gnd gnd CMOSN W=100u L=100u M=1
m95 net-_m102-pad2_ c8 vdd vdd CMOSP W=100u L=100u M=1
m101 a1 c8 b24 b24 CMOSN W=100u L=100u M=1
m96 net-_m100-pad1_ s0 net-_m96-pad3_ net-_m96-pad3_ CMOSN W=100u L=100u M=1
m97 net-_m96-pad3_ s1 net-_m97-pad3_ net-_m97-pad3_ CMOSN W=100u L=100u M=1
m98 net-_m97-pad3_ e2 gnd gnd CMOSN W=100u L=100u M=1
m99 net-_m100-pad1_ s1 vdd vdd CMOSP W=100u L=100u M=1
m100 net-_m100-pad1_ e2 vdd vdd CMOSP W=100u L=100u M=1
m93 net-_m100-pad1_ s0 vdd vdd CMOSP W=100u L=100u M=1
m104 c8 net-_m100-pad1_ vdd vdd CMOSP W=100u L=100u M=1
m103 c8 net-_m100-pad1_ gnd gnd CMOSN W=100u L=100u M=1
.tran 0e-00 0e-00 0e-00
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
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