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Code Model Test: d latch, set-reset latch, frequency divider
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*** analysis type ***
.tran .01s 8s
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*** input sources ***
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vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) )
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vdata2 200 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0)
+ (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) )
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vclk 300 0 DC PWL( (0 0.0) (0.5 0.0) (0.50000000001 1.0)
+ (1.0 1.0) (1.00000000001 0.0)
+ (1.5 0.0) (1.50000000001 1.0)
+ (2.0 1.0) (2.00000000001 0.0)
+ (2.5 0.0) (2.50000000001 1.0)
+ (3.0 1.0) (3.00000000001 0.0)
+ (3.5 0.0) (3.50000000001 1.0)
+ (4.0 1.0) (4.00000000001 0.0)
+ (4.5 0.0) (4.50000000001 1.0)
+ (5.0 1.0) (5.00000000001 0.0)
+ (5.5 0.0) (5.50000000001 1.0)
+ (6.0 1.0) (6.00000000001 0.0)
+ (6.5 0.0) (6.50000000001 1.0)
+ (7.0 1.0) (7.00000000001 0.0)
+ (7.5 0.0) (7.50000000001 1.0) (8.0 1.0) )
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vset 400 0 DC 0.0
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vreset 500 0 DC PWL( (0 0.0) (3.8 0.0) (3.80000000001 1.0) (4 1.0) )
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*** adc_bridge block ***
aconverter [100 200 300 400 500] [1 2 3 4 5] adc_bridge1
.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9
+ rise_delay=1.0e-12 fall_delay=1.0e-12)
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*** d latch block ***
a1 1 3 4 5 10 11 d_dlatch1
.model d_dlatch1 d_dlatch (data_delay=1.0e-6 enable_delay=2.0e-6
+ set_delay=3.0e-6 reset_delay=4.0e-6
+ ic=0
+ rise_delay=5.0e-6 fall_delay=6.0e-6
+ data_load=1.0e-12 enable_load=1.0e-12
+ set_load=1.0e-12 reset_load=1.0e-12)
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*** set-reset latch block ***
a2 1 2 3 4 5 20 21 d_srlatch1
.model d_srlatch1 d_srlatch (sr_delay=1.0e-6 enable_delay=2.0e-6
+ set_delay=3.0e-6 reset_delay=4.0e-6
+ ic=0
+ rise_delay=5.0e-6 fall_delay=6.0e-6
+ sr_load=1.0e-12 enable_load=1.0e-12
+ set_load=1.0e-12 reset_load=1.0e-12)
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*** frequency divider block ***
a3 3 30 d_fdiv1
.model d_fdiv1 d_fdiv (div_factor=3 high_cycles=2
+ i_count=0 rise_delay=1.0e-6 fall_delay=2.0e-6
+ freq_in_load=1.0e-12)
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*** resistors to ground ***
r1 100 0 1k
r2 200 0 1k
r3 300 0 1k
r4 400 0 1k
r5 500 0 1k
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.end
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