Examples - eSim/.git - This repository contain source code for new flow of FreeEDA now know as eSim

Mode	Name	Size
d---------	4_bit_JK_ff	414	log plain
d---------	7805VoltageRegulator	970	log plain
d---------	7812VoltageRegulator	922	log plain
d---------	Analysis_Of_Digital_IC	390	log plain
d---------	Astable555	833	log plain
d---------	BJT_Biascircuit	481	log plain
d---------	BJT_CB_config	465	log plain
d---------	BJT_CE_config	465	log plain
d---------	BJT_Frequency_Response	516	log plain
d---------	BJT_amplifier	506	log plain
d---------	BasicGates	459	log plain
d---------	Clampercircuit	471	log plain
d---------	Clippercircuit	471	log plain
d---------	Differentiator	574	log plain
d---------	Diode_characteristics	527	log plain
d---------	FET_Amplifier	465	log plain
d---------	FET_Characteristic	505	log plain
d---------	FrequencyResponse_JFET	652	log plain
d---------	FullAdder	1038	log plain
d---------	FullwaveRectifier_SCR	780	log plain
d---------	Fullwavebridgerectifier	543	log plain
d---------	Half_Adder	448	log plain
d---------	HalfwaveRectifier_SCR	780	log plain
d---------	Halfwave_Rectifier	503	log plain
d---------	High_Pass_Filter	399	log plain
d---------	Integrator	621	log plain
d---------	Integrator_LM_741	931	log plain
d---------	InvertingAmplifier	773	log plain
d---------	JK_Flipflop	414	log plain
d---------	Low_Pass_Filter	446	log plain
d---------	Monostable555	901	log plain
d---------	NGHDL_Examples	160	log plain
d---------	Parallel_Resonance	470	log plain
d---------	RC	342	log plain
d---------	RL	342	log plain
d---------	RLC	350	log plain
d---------	Series_Resonance	399	log plain
d---------	Transformer	364	log plain
d---------	UJT_Relaxation_Oscillator	805	log plain
d---------	Zener_Characteristic	470	log plain