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path: root/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out
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* c:\users\malli\esim-workspace\4028_test\4028_test.cir

.include 4028.sub
x1 net-_u11-pad5_ net-_u11-pad3_ net-_u11-pad1_ net-_u11-pad8_ net-_u12-pad2_ net-_u11-pad6_ net-_u11-pad7_ ? net-_u12-pad1_ net-_u13-pad5_ net-_u13-pad8_ net-_u13-pad7_ net-_u13-pad6_ net-_u11-pad2_ net-_u11-pad4_ ? 4028
* u13  a0 a1 a2 a3 net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ adc_bridge_4
* u11  net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
* u12  net-_u12-pad1_ net-_u12-pad2_ q8 q9 dac_bridge_2
v2 a1 gnd  dc 0
v1 a0 gnd  dc 5
v3 a2 gnd  dc 5
v4 a3 gnd  dc 0
* u2  q1 plot_v1
* u3  q2 plot_v1
* u4  q3 plot_v1
* u5  q4 plot_v1
* u6  q5 plot_v1
* u7  q6 plot_v1
* u8  q7 plot_v1
* u9  q8 plot_v1
* u10  q9 plot_v1
* u1  q0 plot_v1
* u16  a1 plot_v1
* u15  a0 plot_v1
* u14  a3 plot_v1
* u17  a2 plot_v1
a1 [a0 a1 a2 a3 ] [net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ ] u13
a2 [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] [q0 q1 q2 q3 q4 q5 q6 q7 ] u11
a3 [net-_u12-pad1_ net-_u12-pad2_ ] [q8 q9 ] u12
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u13 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) 
* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
.model u11 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
.model u12 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) 
.tran 10e-03 100e-03 0e-03

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(q1)
plot v(q2)
plot v(q3)
plot v(q4)
plot v(q5)
plot v(q6)
plot v(q7)
plot v(q8)
plot v(q9)
plot v(q0)
plot v(a1)
plot v(a0)
plot v(a3)
plot v(a2)
.endc
.end