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* c:\users\bhargav\esim-workspace\4002_test\4002_test.cir
.include 4002.sub
x1 net-_u2-pad1_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ? ? ? net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ net-_u2-pad2_ ? 4002
* u1 net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4
* u3 net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ adc_bridge_4
* u2 net-_u2-pad1_ net-_u2-pad2_ out1 out2 dac_bridge_2
r5 out1 gnd 1k
r6 out2 gnd 1k
* u9 out1 plot_v1
* u8 out2 plot_v1
* u13 v8 plot_v1
* u10 v7 plot_v1
* u11 v6 plot_v1
* u12 v5 plot_v1
r10 net-_r10-pad1_ v8 1k
r9 net-_r9-pad1_ v7 1k
r8 net-_r8-pad1_ v6 1k
r7 net-_r7-pad1_ v5 1k
v6 v7 gnd dc 0
v5 v8 gnd dc 0
v8 v5 gnd dc 0
v7 v6 gnd dc 5
* u7 v4 plot_v1
* u4 v3 plot_v1
* u6 v2 plot_v1
* u5 v1 plot_v1
r4 v4 net-_r4-pad2_ 1k
r3 v3 net-_r3-pad2_ 1k
r2 v2 net-_r2-pad2_ 1k
r1 v1 net-_r1-pad2_ 1k
v4 v4 gnd dc 0
v3 v3 gnd dc 0
v2 v2 gnd dc 0
v1 v1 gnd dc 0
a1 [net-_r1-pad2_ net-_r2-pad2_ net-_r3-pad2_ net-_r4-pad2_ ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1
a2 [net-_r10-pad1_ net-_r9-pad1_ net-_r8-pad1_ net-_r7-pad1_ ] [net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u3-pad8_ ] u3
a3 [net-_u2-pad1_ net-_u2-pad2_ ] [out1 out2 ] u2
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u3 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
.model u2 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
.tran 10e-03 100e-03 0e-03
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(out1)
plot v(out2)
plot v(v8)
plot v(v7)
plot v(v6)
plot v(v5)
plot v(v4)
plot v(v3)
plot v(v2)
plot v(v1)
.endc
.end
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