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* eeschema netlist version 1.1 (spice format) creation date: thu may 7 15:36:48 2015
* u3 4 5 19 12 28 9 25 d_jkff
v1 2 0 dc 5
v3 1 0 dc 5
v4 33 0 0
v2 3 0 pulse(0 5 0.1m 0.1m 0.1m 20m 40m)
* u5 25 25 19 11 29 21 34 d_jkff
* u7 35 35 19 17 30 22 36 d_jkff
* u10 27 27 19 18 16 23 0 d_jkff
* u6 34 25 35 d_and
* u8 36 35 27 d_and
* u4 26 33 31 32 28 29 30 16 adc_bridge_4
v10 31 0 0
v11 32 0 0
v9 26 0 0
v8 14 0 0
* u2 15 14 10 13 18 17 11 12 adc_bridge_4
v6 10 0 0
v7 13 0 0
v5 15 0 0
* u1 2 3 1 4 19 5 adc_bridge_3
* u9 9 21 22 23 6 7 8 24 dac_bridge_4
r2 0 7 1k
r3 0 8 1k
r4 0 24 1k
r1 0 6 1k
a1 4 5 19 12 28 9 25 u3
a2 25 25 19 11 29 21 34 u5
a3 35 35 19 17 30 22 36 u7
a4 27 27 19 18 16 23 100 u10
a5 [34 25 ] 35 u6
a6 [36 35 ] 27 u8
a7 [26 33 31 32 ] [28 29 30 16 ] u4
a8 [15 14 10 13 ] [18 17 11 12 ] u2
a9 [2 3 1 ] [4 19 5 ] u1
a10 [9 21 22 23 ] [6 7 8 24 ] u9
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u3 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 )
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u5 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 )
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u7 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 )
* Schematic Name: d_jkff, NgSpice Name: d_jkff
.model u10 d_jkff(ic=0 set_delay=1.0e-9 set_load=1.0e-12 reset_load=1.0e-12 clk_delay=1.0e-9 clk_load=1.0e-12 reset_delay=1.0 rise_delay=1.0e-9 jk_load=1.0e-12 fall_delay=1.0e-9 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u6 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Schematic Name: d_and, NgSpice Name: d_and
.model u8 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u4 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u2 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
.model u1 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge
.model u9 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
.tran 10e-03 100e-03 0e-03
* Control Statements
.control
run
plot v(3)
plot v(6)
plot v(7)
plot v(8)
plot v(24)
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
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