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* /home/bhargav/esim-workspace/4_input_or_characteristics/4_input_or_characteristics.cir
.include 4072.sub
* u5 v1 v2 v3 v4 net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ adc_bridge_4
* u7 v8 v7 v6 v5 net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ adc_bridge_4
* u6 net-_u6-pad1_ net-_u6-pad2_ out1 out2 dac_bridge_2
r1 out1 gnd 1k
r2 out2 gnd 1k
* u9 out1 plot_v1
* u8 out2 plot_v1
* u13 v8 plot_v1
* u10 v7 plot_v1
* u11 v6 plot_v1
* u12 v5 plot_v1
v7 v7 gnd dc 0
v8 v8 gnd dc 0
v5 v5 gnd dc 0
v6 v6 gnd dc 0
* u4 v4 plot_v1
* u1 v3 plot_v1
* u3 v2 plot_v1
* u2 v1 plot_v1
v4 v4 gnd dc 0
v3 v3 gnd dc 0
v2 v2 gnd dc 0
v1 v1 gnd dc 0
x1 net-_u6-pad1_ net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ? ? ? net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ net-_u6-pad2_ ? 4072
a1 [v1 v2 v3 v4 ] [net-_u5-pad5_ net-_u5-pad6_ net-_u5-pad7_ net-_u5-pad8_ ] u5
a2 [v8 v7 v6 v5 ] [net-_u7-pad5_ net-_u7-pad6_ net-_u7-pad7_ net-_u7-pad8_ ] u7
a3 [net-_u6-pad1_ net-_u6-pad2_ ] [out1 out2 ] u6
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u5 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
.model u7 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
.model u6 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
.tran 1e-03 10e-03 0e-03
* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot v(out1)
plot v(out2)
plot v(v8)
plot v(v7)
plot v(v6)
plot v(v5)
plot v(v4)
plot v(v3)
plot v(v2)
plot v(v1)
.endc
.end
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