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This repository contain source code for new flow of FreeEDA now know as eSim
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Author
2023-09-02
Added the Project select warning dialog box for all the features
v2.4
Sumanto Kar
2023-09-02
Merge branch 'master' into master
Sumanto Kar
2023-08-19
Merge branch 'FOSSEE:master' into master
SangaviGR
2023-06-29
removed kicad online mode switching
rahulp13
2023-06-28
Made the text in TerminalUi log console selectable
Pranav P
2023-06-20
subcircuiteditor method modified
Sangavi GR
2023-06-13
Merge branch 'master' into sky130-dev
Rahul P
2023-06-13
maker module flake8 compliant & added docstrings
rahulp13
2023-06-13
removed SoC gen. button
rahulp13
2023-06-11
fixed multiple signal issue with cancel sim.
rahulp13
2023-06-07
sim. process switched to qt slot-signal mech. & report errors
rahulp13
2023-06-07
sync cancel and redo simulation features
rahulp13
2023-06-03
Updated docstrings for sphinx documentation
Pranav P
2023-06-03
Got rid of simulationEssentials
Pranav P
2023-06-01
PR fixes
Pranav P
2023-06-01
Changed title names of docker tabs
Pranav P
2023-06-01
Added docstrings to the TerminalUi class
Pranav P
2023-06-01
Changed style in accordance with flake8
Pranav P
2023-06-01
Fixes for PR
Pranav P
2023-05-25
Now loads TerminalUi from ui file
Pranav P
2023-05-25
Added sphinx docstring documentation to newly added functions and removed som...
Pranav P
2023-05-24
Readded old xterm check and commented it out
Pranav P
2023-05-24
Reduced the number of methods in TerminalUi
Pranav P
2023-05-24
Changed the name progressBar to TerminalUi
Pranav P
2023-05-24
Reduced passage of functions between objects via simulationEssentials
Pranav P
2023-05-23
Changed the polling approach to check ngspice simulation completion
Pranav P
2023-05-19
Added redo simulation button to progressbar window
Pranav P
2023-05-15
Changed simulation status colour and dark mode icon path
Pranav P
2023-05-07
Removed unnecessary print statements used for debugging
Pranav P
2023-05-07
Mentions whether simulation successful or not
Pranav P
2023-05-04
Disabled multiple simulations
Pranav P
2023-05-04
Enabled cancel simulation button
Pranav P
2023-05-03
Changed ngspice simulation progressbar design
Pranav P
2023-04-08
Hopefully fixed a bug which could have been a racing condition
Pranav P
2023-04-07
Added progress bar, QtTimer and removed the plots
Pranav P
2022-09-18
Merge branch 'master' into sky130-dev
v2.3
rahulp13
2022-09-17
fix circuit component element out of range crash
rahulp13
2022-09-17
fix file open issue due to #210
rahulp13
2022-09-17
Moved gen-soc button to menu bar
rahulp13
2022-07-05
Resolved Project Files Refresh Problem
PatelVatsalB21
2022-02-28
Refactored display names in NgVeri UI
rahulp13
2022-02-22
Fixed typos and resolved flake8 issues
rahulp13
2022-02-22
Restructured config paths and other path issues
rahulp13
2022-02-22
Ignore 'xterm' process checking on Windows OS
rahulp13
2022-02-10
Cleaned up merge conflict messages
rahulp13
2022-01-29
Resolved Conflicts
Eyantra698Sumanto
2022-01-25
Adding the makerchip options in frontEnd
Eyantra698Sumanto
2022-01-25
revert simulation wait count to 10
Eyantra698Sumanto
2022-01-25
Fixed netlist name
Eyantra698Sumanto
2021-08-25
Resolved pep8 issue in DockArea.py
Eyantra698Sumanto
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