| Age | Commit message (Expand) | Author |
|---|---|---|
| 2025-06-30 | Deleted Tristate Buffer Verilog code | GanderlaChaithanya |
| 2025-06-30 | Verilog Code for Tri State Buffer for the Subcircuit - 163501 | GanderlaChaithanya |
| 2025-06-30 | ic163501 - 10-Bit Registered Transciever | GanderlaChaithanya |
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index : eSim/.git | |
| This repository contain source code for new flow of FreeEDA now know as eSim |
| summaryrefslogtreecommitdiff |