diff options
Diffstat (limited to 'src/SubcircuitLibrary')
41 files changed, 2365 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/diac/analysis b/src/SubcircuitLibrary/diac/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/diac/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/diac/diac-cache.lib b/src/SubcircuitLibrary/diac/diac-cache.lib new file mode 100644 index 00000000..b15fdeec --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac-cache.lib @@ -0,0 +1,67 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/diac/diac.bak b/src/SubcircuitLibrary/diac/diac.bak new file mode 100644 index 00000000..16009984 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.bak @@ -0,0 +1,138 @@ +EESchema Schematic File Version 2 date 09/22/14 16:36:31
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:diac-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 sep 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 4150 2750 4150 3450
+Connection ~ 4400 3750
+Wire Wire Line
+ 4900 4250 4900 4450
+Wire Wire Line
+ 4900 4450 4400 4450
+Wire Wire Line
+ 4400 4450 4400 3450
+Wire Wire Line
+ 5200 3400 5200 4050
+Connection ~ 4600 3400
+Wire Wire Line
+ 4600 4050 4600 2750
+Wire Wire Line
+ 4600 2750 4150 2750
+Wire Wire Line
+ 4150 3250 4150 3600
+Wire Wire Line
+ 4400 3450 4150 3450
+Connection ~ 4150 3450
+Wire Wire Line
+ 4400 3750 4900 3750
+Wire Wire Line
+ 4900 3750 4900 3600
+Wire Wire Line
+ 4150 4100 4150 4300
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5417D647
+P 4150 4300
+F 0 "#FLG01" H 4150 4570 30 0001 C CNN
+F 1 "PWR_FLAG" H 4150 4530 30 0000 C CNN
+ 1 4150 4300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U3
+U 2 1 5417D62C
+P 5450 3400
+F 0 "U3" H 5450 3350 30 0000 C CNN
+F 1 "PORT" H 5450 3400 30 0000 C CNN
+ 2 5450 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U3
+U 1 1 5417D624
+P 4150 2500
+F 0 "U3" H 4150 2450 30 0000 C CNN
+F 1 "PORT" H 4150 2500 30 0000 C CNN
+ 1 4150 2500
+ 0 1 1 0
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5417D5DC
+P 4150 4300
+F 0 "#PWR02" H 4150 4300 30 0001 C CNN
+F 1 "GND" H 4150 4230 30 0001 C CNN
+ 1 4150 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L ANALOGSWITCH U2
+U 1 1 5417D537
+P 4900 4050
+F 0 "U2" H 4700 4100 30 0000 C CNN
+F 1 "ANALOGSWITCH" H 4900 4050 30 0000 C CNN
+ 1 4900 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L ANALOGSWITCH U1
+U 1 1 5417D530
+P 4900 3400
+F 0 "U1" H 4700 3450 30 0000 C CNN
+F 1 "ANALOGSWITCH" H 4900 3400 30 0000 C CNN
+ 1 4900 3400
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/diac/diac.cir b/src/SubcircuitLibrary/diac/diac.cir new file mode 100644 index 00000000..91629b91 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir @@ -0,0 +1,13 @@ +* /opt/eSim/src/SubcircuitLibrary/diac/diac.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:35:49 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 1 2 PORT +U1 1 1 2 aswitch +U2 1 1 2 aswitch + +.end diff --git a/src/SubcircuitLibrary/diac/diac.cir.ckt b/src/SubcircuitLibrary/diac/diac.cir.ckt new file mode 100644 index 00000000..e89f9cfb --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: 09/22/14 16:36:23
+
+u3 1 2 port
+* Analog Switch analogswitch
+* Analog Switch analogswitch
+a1 1 (1 2) u2
+.model u2 aswitch(cntl_on=-25 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
+a2 1 (1 2) u1
+.model u1 aswitch(cntl_on=25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/diac/diac.cir.out b/src/SubcircuitLibrary/diac/diac.cir.out new file mode 100644 index 00000000..a1e31f14 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir.out @@ -0,0 +1,21 @@ +* /opt/esim/src/subcircuitlibrary/diac/diac.cir + +* u3 1 2 port +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 (1 2) u1 +a2 1 (1 2) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) + +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/diac/diac.cir.out~ b/src/SubcircuitLibrary/diac/diac.cir.out~ new file mode 100644 index 00000000..89cc8142 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir.out~ @@ -0,0 +1,24 @@ +* /opt/esim/src/subcircuitlibrary/diac/diac.cir + +* u3 1 2 port +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 [1 2 ] u1 +a2 1 [1 2 ] u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/diac/diac.pro b/src/SubcircuitLibrary/diac/diac.pro new file mode 100644 index 00000000..c8563047 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.pro @@ -0,0 +1,45 @@ +update=Tue Dec 8 14:06:36 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=eSim_Analog +LibName33=eSim_Devices +LibName34=eSim_Digital +LibName35=eSim_Hybrid +LibName36=eSim_Miscellaneous +LibName37=eSim_Sources +LibName38=eSim_Subckt +LibName39=eSim_User diff --git a/src/SubcircuitLibrary/diac/diac.sch b/src/SubcircuitLibrary/diac/diac.sch new file mode 100644 index 00000000..163665e7 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.sch @@ -0,0 +1,148 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 sep 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4150 2750 4150 4300 +Connection ~ 4400 3750 +Wire Wire Line + 4400 4450 5050 4450 +Wire Wire Line + 4400 4450 4400 3450 +Wire Wire Line + 5500 3350 5500 4050 +Connection ~ 4600 3400 +Wire Wire Line + 4600 4050 4600 2750 +Wire Wire Line + 4600 2750 4150 2750 +Wire Wire Line + 4400 3450 4150 3450 +Connection ~ 4150 3450 +Wire Wire Line + 4400 3750 5050 3750 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5417D647 +P 4150 4300 +F 0 "#FLG01" H 4150 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 4150 4530 30 0000 C CNN +F 2 "" H 4150 4300 60 0001 C CNN +F 3 "" H 4150 4300 60 0001 C CNN + 1 4150 4300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 2 1 5417D62C +P 5750 3350 +F 0 "U3" H 5750 3300 30 0000 C CNN +F 1 "PORT" H 5750 3350 30 0000 C CNN +F 2 "" H 5750 3350 60 0001 C CNN +F 3 "" H 5750 3350 60 0001 C CNN + 2 5750 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 1 1 5417D624 +P 4150 2500 +F 0 "U3" H 4150 2450 30 0000 C CNN +F 1 "PORT" H 4150 2500 30 0000 C CNN +F 2 "" H 4150 2500 60 0001 C CNN +F 3 "" H 4150 2500 60 0001 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5417D5DC +P 4150 4300 +F 0 "#PWR02" H 4150 4300 30 0001 C CNN +F 1 "GND" H 4150 4230 30 0001 C CNN +F 2 "" H 4150 4300 60 0001 C CNN +F 3 "" H 4150 4300 60 0001 C CNN + 1 4150 4300 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 56669812 +P 4600 3550 +F 0 "U1" H 5050 3850 60 0000 C CNN +F 1 "aswitch" H 5050 3750 60 0000 C CNN +F 2 "" H 5050 3650 60 0000 C CNN +F 3 "" H 5050 3650 60 0000 C CNN + 1 4600 3550 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U2 +U 1 1 5666987C +P 4600 4200 +F 0 "U2" H 5050 4500 60 0000 C CNN +F 1 "aswitch" H 5050 4400 60 0000 C CNN +F 2 "" H 5050 4300 60 0000 C CNN +F 3 "" H 5050 4300 60 0000 C CNN + 1 4600 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 4450 5050 4300 +Wire Wire Line + 5050 3750 5050 3650 +Wire Wire Line + 5500 4050 5450 4050 +Wire Wire Line + 5500 3400 5450 3400 +Connection ~ 5500 3400 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/diac/diac.sub b/src/SubcircuitLibrary/diac/diac.sub new file mode 100644 index 00000000..7f28ecc2 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.sub @@ -0,0 +1,15 @@ +* Subcircuit diac +.subckt diac 1 2 +* /opt/esim/src/subcircuitlibrary/diac/diac.cir +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 (1 2) u1 +a2 1 (1 2) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) + +* Control Statements + +.ends diac diff --git a/src/SubcircuitLibrary/diac/diac.sub~ b/src/SubcircuitLibrary/diac/diac.sub~ new file mode 100644 index 00000000..43c2d279 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.sub~ @@ -0,0 +1,18 @@ +* Subcircuit diac +.subckt diac 1 2 +* /opt/esim/src/subcircuitlibrary/diac/diac.cir +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 [1 2 ] u1 +a2 1 [1 2 ] u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +* Control Statements + +.ends diac
\ No newline at end of file diff --git a/src/SubcircuitLibrary/diac/diac_Previous_Values.xml b/src/SubcircuitLibrary/diac/diac_Previous_Values.xml new file mode 100644 index 00000000..96df431c --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">25</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-25</field10></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/D.lib b/src/SubcircuitLibrary/scr/D.lib new file mode 100755 index 00000000..ef18bb50 --- /dev/null +++ b/src/SubcircuitLibrary/scr/D.lib @@ -0,0 +1,20 @@ +.MODEL D1N750 D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ Bv=8.1 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=880.5E-18 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/PowerDiode.lib b/src/SubcircuitLibrary/scr/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/src/SubcircuitLibrary/scr/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/analysis b/src/SubcircuitLibrary/scr/analysis new file mode 100644 index 00000000..687c71ec --- /dev/null +++ b/src/SubcircuitLibrary/scr/analysis @@ -0,0 +1 @@ +.tran 0e-12 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/scr-cache.lib b/src/SubcircuitLibrary/scr/scr-cache.lib new file mode 100644 index 00000000..24105a8a --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# DIODE +# +DEF DIODE D 0 40 N N 1 F N +F0 "D" 0 100 40 H V C CNN +F1 "DIODE" 0 -100 40 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + D? + S* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -200 0 150 R 40 40 1 1 P +X K 2 200 0 150 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/scr/scr.bak b/src/SubcircuitLibrary/scr/scr.bak new file mode 100644 index 00000000..58b985d9 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.bak @@ -0,0 +1,243 @@ +EESchema Schematic File Version 2 +LIBS:analogSpice +LIBS:analogXSpice +LIBS:convergenceAidSpice +LIBS:converterSpice +LIBS:digitalSpice +LIBS:digitalXSpice +LIBS:measurementSpice +LIBS:portSpice +LIBS:sourcesSpice +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:scr-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 aug 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3600 3250 3600 3150 +Connection ~ 5550 4950 +Wire Wire Line + 5800 3900 5800 3850 +Wire Wire Line + 5800 3850 6150 3850 +Wire Wire Line + 6150 3850 6150 4950 +Wire Wire Line + 6150 4950 3600 4950 +Connection ~ 4300 4950 +Wire Wire Line + 4300 4950 4300 4050 +Wire Wire Line + 4300 4050 3850 4050 +Wire Wire Line + 4700 5950 4700 5450 +Wire Wire Line + 4250 5950 4250 5500 +Connection ~ 4250 4950 +Wire Wire Line + 4250 5000 4250 4950 +Wire Wire Line + 5550 3600 5550 3450 +Wire Wire Line + 5550 4950 5550 4250 +Wire Wire Line + 3600 4950 3600 4400 +Wire Wire Line + 3600 2650 3600 2300 +Wire Wire Line + 3600 2300 3150 2300 +Wire Wire Line + 3600 4150 3600 4300 +Wire Wire Line + 5550 4150 5550 4000 +Wire Wire Line + 5550 2550 5550 2250 +Wire Wire Line + 4700 5050 4700 4950 +Connection ~ 4700 4950 +Wire Wire Line + 6650 2000 6650 5950 +Connection ~ 4700 5950 +Wire Wire Line + 3850 4650 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 4250 5950 +Wire Wire Line + 5800 4500 5800 5950 +Connection ~ 5800 5950 +$Comp +L PORT U2 +U 3 1 53F4C93D +P 6650 2250 +F 0 "U2" H 6650 2200 30 0000 C CNN +F 1 "PORT" H 6650 2250 30 0000 C CNN +F 2 "" H 6650 2250 60 0001 C CNN +F 3 "" H 6650 2250 60 0001 C CNN + 3 6650 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 53F4C934 +P 2900 2300 +F 0 "U2" H 2900 2250 30 0000 C CNN +F 1 "PORT" H 2900 2300 30 0000 C CNN +F 2 "" H 2900 2300 60 0001 C CNN +F 3 "" H 2900 2300 60 0001 C CNN + 2 2900 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 1 1 53F4C92A +P 6400 4950 +F 0 "U2" H 6400 4900 30 0000 C CNN +F 1 "PORT" H 6400 4950 30 0000 C CNN +F 2 "" H 6400 4950 60 0001 C CNN +F 3 "" H 6400 4950 60 0001 C CNN + 1 6400 4950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 53F4C735 +P 5750 4200 +F 0 "F2" H 5550 4300 50 0000 C CNN +F 1 "100" H 5550 4150 50 0000 C CNN +F 2 "" H 5750 4200 60 0001 C CNN +F 3 "" H 5750 4200 60 0001 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 53F4C6D9 +P 5550 3800 +F 0 "D1" H 5550 3900 40 0000 C CNN +F 1 "D" H 5550 3700 40 0000 C CNN +F 2 "" H 5550 3800 60 0001 C CNN +F 3 "" H 5550 3800 60 0001 C CNN + 1 5550 3800 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 53F4C6C2 +P 4700 5250 +F 0 "C1" H 4750 5350 50 0000 L CNN +F 1 "10u" H 4750 5150 50 0000 L CNN +F 2 "" H 4700 5250 60 0001 C CNN +F 3 "" H 4700 5250 60 0001 C CNN + 1 4700 5250 + 1 0 0 -1 +$EndComp +$Comp +L R R2 +U 1 1 53F4C6BB +P 4250 5250 +F 0 "R2" V 4330 5250 50 0000 C CNN +F 1 "1" V 4250 5250 50 0000 C CNN +F 2 "" H 4250 5250 60 0001 C CNN +F 3 "" H 4250 5250 60 0001 C CNN + 1 4250 5250 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 53F4C67F +P 3800 4350 +F 0 "F1" H 3600 4450 50 0000 C CNN +F 1 "10" H 3600 4300 50 0000 C CNN +F 2 "" H 3800 4350 60 0001 C CNN +F 3 "" H 3800 4350 60 0001 C CNN + 1 3800 4350 + 0 1 1 0 +$EndComp +$Comp +L R R1 +U 1 1 53F4C5C9 +P 3600 2900 +F 0 "R1" V 3680 2900 50 0000 C CNN +F 1 "50" V 3600 2900 50 0000 C CNN +F 2 "" H 3600 2900 60 0001 C CNN +F 3 "" H 3600 2900 60 0001 C CNN + 1 3600 2900 + 1 0 0 -1 +$EndComp +$Comp +L dc v1 +U 1 1 565DBF58 +P 3600 3700 +F 0 "v1" H 3400 3800 60 0000 C CNN +F 1 "dc" H 3400 3650 60 0000 C CNN +F 2 "R1" H 3300 3700 60 0000 C CNN +F 3 "" H 3600 3700 60 0000 C CNN + 1 3600 3700 + 1 0 0 -1 +$EndComp +$Comp +L dc v2 +U 1 1 565DC066 +P 5550 3000 +F 0 "v2" H 5350 3100 60 0000 C CNN +F 1 "dc" H 5350 2950 60 0000 C CNN +F 2 "R1" H 5250 3000 60 0000 C CNN +F 3 "" H 5550 3000 60 0000 C CNN + 1 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 565DC87E +P 6400 2100 +F 0 "U1" H 6850 2400 60 0000 C CNN +F 1 "aswitch" H 6850 2300 60 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 1 6400 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2000 6650 2000 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/scr/scr.cir b/src/SubcircuitLibrary/scr/scr.cir new file mode 100644 index 00000000..4b279764 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir @@ -0,0 +1,20 @@ +* /opt/eSim/src/SubcircuitLibrary/scr/scr.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:47:20 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 3 7 1 PORT +F2 3 9 2 3 100 +D1 5 2 D +C1 3 9 10u +F1 3 9 4 3 10 +v1 8 4 dc +v2 6 5 dc +U1 9 1 6 aswitch +R1 7 8 50 +R2 3 9 1 + +.end diff --git a/src/SubcircuitLibrary/scr/scr.cir.ckt b/src/SubcircuitLibrary/scr/scr.cir.ckt new file mode 100644 index 00000000..b0e218fd --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir.ckt @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: 08/21/14 11:07:22
+.include diode.lib
+
+u2 5 8 1 port
+* f2
+* Analog Switch analogswitch
+d1 4 2 diode
+v2 3 4 dc 0
+c1 5 6 10u
+r2 5 6 1
+* f1
+v1 9 7 dc 0
+r1 8 9 50
+Vf2 2 5 0
+f2 5 6 Vf2 100
+Vf1 7 5 0
+f1 5 6 Vf1 10
+a1 6 (1 3) u1
+.model u1 aswitch(cntl_on=0.25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/scr/scr.cir.out b/src/SubcircuitLibrary/scr/scr.cir.out new file mode 100644 index 00000000..d600f25d --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir.out @@ -0,0 +1,29 @@ +* /opt/esim/src/subcircuitlibrary/scr/scr.cir + +.include PowerDiode.lib +* u2 3 7 1 port +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/scr/scr.cir.out~ b/src/SubcircuitLibrary/scr/scr.cir.out~ new file mode 100644 index 00000000..d600f25d --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.cir.out~ @@ -0,0 +1,29 @@ +* /opt/esim/src/subcircuitlibrary/scr/scr.cir + +.include PowerDiode.lib +* u2 3 7 1 port +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +.tran 0e-12 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/scr/scr.pro b/src/SubcircuitLibrary/scr/scr.pro new file mode 100644 index 00000000..fc4ca966 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.pro @@ -0,0 +1,44 @@ +update=Tue Dec 8 15:45:12 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Sources +LibName7=eSim_Subckt +LibName8=eSim_User +LibName9=power +LibName10=device +LibName11=transistors +LibName12=conn +LibName13=linear +LibName14=regul +LibName15=74xx +LibName16=cmos4000 +LibName17=adc-dac +LibName18=memory +LibName19=xilinx +LibName20=special +LibName21=microcontrollers +LibName22=dsp +LibName23=microchip +LibName24=analog_switches +LibName25=motorola +LibName26=texas +LibName27=intel +LibName28=audio +LibName29=interface +LibName30=digital-audio +LibName31=philips +LibName32=display +LibName33=cypress +LibName34=siliconi +LibName35=opto +LibName36=atmel +LibName37=contrib +LibName38=valves diff --git a/src/SubcircuitLibrary/scr/scr.sch b/src/SubcircuitLibrary/scr/scr.sch new file mode 100644 index 00000000..1f23ec65 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.sch @@ -0,0 +1,241 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:scr-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "21 aug 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3600 3250 3600 3150 +Connection ~ 5550 4950 +Wire Wire Line + 5800 3900 5800 3850 +Wire Wire Line + 5800 3850 6150 3850 +Wire Wire Line + 6150 3850 6150 4950 +Wire Wire Line + 6150 4950 3600 4950 +Connection ~ 4300 4950 +Wire Wire Line + 4300 4950 4300 4050 +Wire Wire Line + 4300 4050 3850 4050 +Wire Wire Line + 4700 5400 4700 5950 +Wire Wire Line + 4250 5950 4250 5500 +Connection ~ 4250 4950 +Wire Wire Line + 4250 4950 4250 5200 +Wire Wire Line + 5550 3600 5550 3450 +Wire Wire Line + 5550 4950 5550 4250 +Wire Wire Line + 3600 4950 3600 4400 +Wire Wire Line + 3600 2300 3600 2850 +Wire Wire Line + 3600 2300 3150 2300 +Wire Wire Line + 3600 4150 3600 4300 +Wire Wire Line + 5550 4150 5550 4000 +Wire Wire Line + 5550 2550 5550 2250 +Wire Wire Line + 4700 4950 4700 5100 +Connection ~ 4700 4950 +Wire Wire Line + 6650 2000 6650 5950 +Connection ~ 4700 5950 +Wire Wire Line + 3850 4650 3850 5950 +Wire Wire Line + 3850 5950 6650 5950 +Connection ~ 4250 5950 +Wire Wire Line + 5800 4500 5800 5950 +Connection ~ 5800 5950 +$Comp +L PORT U2 +U 3 1 53F4C93D +P 6650 2250 +F 0 "U2" H 6650 2200 30 0000 C CNN +F 1 "PORT" H 6650 2250 30 0000 C CNN +F 2 "" H 6650 2250 60 0001 C CNN +F 3 "" H 6650 2250 60 0001 C CNN + 3 6650 2250 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 53F4C934 +P 2900 2300 +F 0 "U2" H 2900 2250 30 0000 C CNN +F 1 "PORT" H 2900 2300 30 0000 C CNN +F 2 "" H 2900 2300 60 0001 C CNN +F 3 "" H 2900 2300 60 0001 C CNN + 2 2900 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U2 +U 1 1 53F4C92A +P 6400 4950 +F 0 "U2" H 6400 4900 30 0000 C CNN +F 1 "PORT" H 6400 4950 30 0000 C CNN +F 2 "" H 6400 4950 60 0001 C CNN +F 3 "" H 6400 4950 60 0001 C CNN + 1 6400 4950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 53F4C735 +P 5750 4200 +F 0 "F2" H 5550 4300 50 0000 C CNN +F 1 "100" H 5550 4150 50 0000 C CNN +F 2 "" H 5750 4200 60 0001 C CNN +F 3 "" H 5750 4200 60 0001 C CNN + 1 5750 4200 + 0 1 1 0 +$EndComp +$Comp +L DIODE D1 +U 1 1 53F4C6D9 +P 5550 3800 +F 0 "D1" H 5550 3900 40 0000 C CNN +F 1 "D" H 5550 3700 40 0000 C CNN +F 2 "" H 5550 3800 60 0001 C CNN +F 3 "" H 5550 3800 60 0001 C CNN + 1 5550 3800 + 0 1 1 0 +$EndComp +$Comp +L C C1 +U 1 1 53F4C6C2 +P 4700 5250 +F 0 "C1" H 4750 5350 50 0000 L CNN +F 1 "10u" H 4750 5150 50 0000 L CNN +F 2 "" H 4700 5250 60 0001 C CNN +F 3 "" H 4700 5250 60 0001 C CNN + 1 4700 5250 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 53F4C67F +P 3800 4350 +F 0 "F1" H 3600 4450 50 0000 C CNN +F 1 "10" H 3600 4300 50 0000 C CNN +F 2 "" H 3800 4350 60 0001 C CNN +F 3 "" H 3800 4350 60 0001 C CNN + 1 3800 4350 + 0 1 1 0 +$EndComp +$Comp +L dc v1 +U 1 1 565DBF58 +P 3600 3700 +F 0 "v1" H 3400 3800 60 0000 C CNN +F 1 "dc" H 3400 3650 60 0000 C CNN +F 2 "R1" H 3300 3700 60 0000 C CNN +F 3 "" H 3600 3700 60 0000 C CNN + 1 3600 3700 + 1 0 0 -1 +$EndComp +$Comp +L dc v2 +U 1 1 565DC066 +P 5550 3000 +F 0 "v2" H 5350 3100 60 0000 C CNN +F 1 "dc" H 5350 2950 60 0000 C CNN +F 2 "R1" H 5250 3000 60 0000 C CNN +F 3 "" H 5550 3000 60 0000 C CNN + 1 5550 3000 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 565DC87E +P 6400 2100 +F 0 "U1" H 6850 2400 60 0000 C CNN +F 1 "aswitch" H 6850 2300 60 0000 C CNN +F 2 "" H 6850 2200 60 0000 C CNN +F 3 "" H 6850 2200 60 0000 C CNN + 1 6400 2100 + -1 0 0 1 +$EndComp +Wire Wire Line + 5950 2000 6650 2000 +$Comp +L R R1 +U 1 1 5666B019 +P 3550 2950 +F 0 "R1" H 3600 3080 50 0000 C CNN +F 1 "50" H 3600 3000 50 0000 C CNN +F 2 "" H 3600 2930 30 0000 C CNN +F 3 "" V 3600 3000 30 0000 C CNN + 1 3550 2950 + 0 1 1 0 +$EndComp +$Comp +L R R2 +U 1 1 5666B17A +P 4200 5300 +F 0 "R2" H 4250 5430 50 0000 C CNN +F 1 "1" H 4250 5350 50 0000 C CNN +F 2 "" H 4250 5280 30 0000 C CNN +F 3 "" V 4250 5350 30 0000 C CNN + 1 4200 5300 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/scr/scr.sub b/src/SubcircuitLibrary/scr/scr.sub new file mode 100644 index 00000000..398c8921 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.sub @@ -0,0 +1,23 @@ +* Subcircuit scr +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.include PowerDiode.lib +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 (1 6) u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr diff --git a/src/SubcircuitLibrary/scr/scr.sub~ b/src/SubcircuitLibrary/scr/scr.sub~ new file mode 100644 index 00000000..0fdddbf4 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr.sub~ @@ -0,0 +1,23 @@ +* Subcircuit scr +.subckt scr 3 7 1 +* /opt/esim/src/subcircuitlibrary/scr/scr.cir +.include PowerDiode.lib +* f2 +d1 5 2 PowerDiode +c1 3 9 10u +* f1 +v1 8 4 dc 0 +v2 6 5 dc 0 +* u1 9 1 6 aswitch +r1 7 8 50 +r2 3 9 1 +Vf2 2 3 0 +f2 3 9 Vf2 100 +Vf1 4 3 0 +f1 3 9 Vf1 10 +a1 9 [1 6 ] u1 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.0 cntl_on=1.0 r_on=1.0 r_off=1.0e12 ) +* Control Statements + +.ends scr
\ No newline at end of file diff --git a/src/SubcircuitLibrary/scr/scr_Previous_Values.xml b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml new file mode 100644 index 00000000..8ff6e8d3 --- /dev/null +++ b/src/SubcircuitLibrary/scr/scr_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v2 name="Source type">dc<field1 name="Value">0</field1></v2></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)" /><field3 name="Enter OFF Resistance (default=1.0e12)" /><field4 name="Enter ON Resistance (default=1.0)" /><field5 name="Enter Control ON value(default=1.0)" /></u1></model><devicemodel><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ps</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/src/SubcircuitLibrary/triac/.triac.s.swp b/src/SubcircuitLibrary/triac/.triac.s.swp Binary files differnew file mode 100644 index 00000000..1a4c2d0e --- /dev/null +++ b/src/SubcircuitLibrary/triac/.triac.s.swp diff --git a/src/SubcircuitLibrary/triac/.triac.sub.swp b/src/SubcircuitLibrary/triac/.triac.sub.swp Binary files differnew file mode 100644 index 00000000..521ce758 --- /dev/null +++ b/src/SubcircuitLibrary/triac/.triac.sub.swp diff --git a/src/SubcircuitLibrary/triac/PowerDiode.lib b/src/SubcircuitLibrary/triac/PowerDiode.lib new file mode 100644 index 00000000..a2f61dce --- /dev/null +++ b/src/SubcircuitLibrary/triac/PowerDiode.lib @@ -0,0 +1,20 @@ +.MODEL PowerDiode D( ++ Vj=.75 ++ Nbvl=14.976 ++ Cjo=175p ++ Rs=.25 ++ Isr=1.859n ++ Eg=1.11 ++ M=.5516 ++ Nbv=1.6989 ++ N=1 ++ Tbv1=-21.277u ++ bv=1800 ++ Fc=.5 ++ Ikf=0 ++ Nr=2 ++ Ibv=20.245m ++ Is=2.2E-15 ++ Xti=3 ++ Ibvl=1.9556m +)
\ No newline at end of file diff --git a/src/SubcircuitLibrary/triac/analysis b/src/SubcircuitLibrary/triac/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/triac/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/triac/triac-cache.lib b/src/SubcircuitLibrary/triac/triac-cache.lib new file mode 100644 index 00000000..0466a3e6 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# CCCS +# +DEF CCCS F 0 40 Y Y 1 F N +F0 "F" 0 150 50 H V C CNN +F1 "CCCS" -200 -50 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +S -100 100 100 -100 0 1 0 N +X + 1 -300 50 200 R 35 35 1 1 P +X - 2 300 50 200 L 35 35 1 1 P +X +c 3 -50 -200 100 U 35 35 1 1 P +X -c 4 50 -200 100 U 35 35 1 1 P +ENDDRAW +ENDDEF +# +# D +# +DEF D D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "D" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + Diode_* + D-Pak_TO252AA + *SingleDiode + *_Diode_* + *SingleDiode* +$ENDFPLIST +DRAW +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/triac/triac.bak b/src/SubcircuitLibrary/triac/triac.bak new file mode 100644 index 00000000..f30533a0 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.bak @@ -0,0 +1,308 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:triac-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 sep 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U3 +U 3 1 541D1606 +P 1250 1750 +F 0 "U3" H 1250 1700 30 0000 C CNN +F 1 "PORT" H 1250 1750 30 0000 C CNN +F 2 "" H 1250 1750 60 0001 C CNN +F 3 "" H 1250 1750 60 0001 C CNN + 3 1250 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 2 1 541D1601 +P 1300 900 +F 0 "U3" H 1300 850 30 0000 C CNN +F 1 "PORT" H 1300 900 30 0000 C CNN +F 2 "" H 1300 900 60 0001 C CNN +F 3 "" H 1300 900 60 0001 C CNN + 2 1300 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 1 1 541D15F6 +P 1150 4050 +F 0 "U3" H 1150 4000 30 0000 C CNN +F 1 "PORT" H 1150 4050 30 0000 C CNN +F 2 "" H 1150 4050 60 0001 C CNN +F 3 "" H 1150 4050 60 0001 C CNN + 1 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F3 +U 1 1 541D1417 +P 6250 3100 +F 0 "F3" H 6050 3200 50 0000 C CNN +F 1 "10" H 6050 3050 50 0000 C CNN +F 2 "" H 6250 3100 60 0001 C CNN +F 3 "" H 6250 3100 60 0001 C CNN + 1 6250 3100 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 541D13FB +P 6050 1950 +F 0 "v3" H 5850 2050 60 0000 C CNN +F 1 "DC" H 5850 1900 60 0000 C CNN +F 2 "R1" H 5750 1950 60 0000 C CNN +F 3 "" H 6050 1950 60 0001 C CNN + 1 6050 1950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 541D13A3 +P 3900 2550 +F 0 "F2" H 3700 2650 50 0000 C CNN +F 1 "10" H 3700 2500 50 0000 C CNN +F 2 "" H 3900 2550 60 0001 C CNN +F 3 "" H 3900 2550 60 0001 C CNN + 1 3900 2550 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 541D1398 +P 3700 1850 +F 0 "v2" H 3500 1950 60 0000 C CNN +F 1 "DC" H 3500 1800 60 0000 C CNN +F 2 "R1" H 3400 1850 60 0000 C CNN +F 3 "" H 3700 1850 60 0001 C CNN + 1 3700 1850 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 541D137C +P 3300 4350 +F 0 "C1" H 3350 4450 50 0000 L CNN +F 1 "10u" H 3350 4250 50 0000 L CNN +F 2 "" H 3300 4350 60 0001 C CNN +F 3 "" H 3300 4350 60 0001 C CNN + 1 3300 4350 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 541D1363 +P 2100 3600 +F 0 "F1" H 1900 3700 50 0000 C CNN +F 1 "100" H 1900 3550 50 0000 C CNN +F 2 "" H 2100 3600 60 0001 C CNN +F 3 "" H 2100 3600 60 0001 C CNN + 1 2100 3600 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 541D1357 +P 1900 2900 +F 0 "v1" H 1700 3000 60 0000 C CNN +F 1 "DC" H 1700 2850 60 0000 C CNN +F 2 "R1" H 1600 2900 60 0000 C CNN +F 3 "" H 1900 2900 60 0001 C CNN + 1 1900 2900 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 56669B8A +P 4600 1100 +F 0 "U1" H 5050 1400 60 0000 C CNN +F 1 "aswitch" H 5050 1300 60 0000 C CNN +F 2 "" H 5050 1200 60 0000 C CNN +F 3 "" H 5050 1200 60 0000 C CNN + 1 4600 1100 + -1 0 0 1 +$EndComp +$Comp +L aswitch U2 +U 1 1 56669DB5 +P 6400 1350 +F 0 "U2" H 6850 1650 60 0000 C CNN +F 1 "aswitch" H 6850 1550 60 0000 C CNN +F 2 "" H 6850 1450 60 0000 C CNN +F 3 "" H 6850 1450 60 0000 C CNN + 1 6400 1350 + 1 0 0 -1 +$EndComp +Connection ~ 4600 900 +Wire Wire Line + 4600 1250 4600 900 +Wire Wire Line + 1900 1750 1500 1750 +Connection ~ 6300 4900 +Wire Wire Line + 6300 3400 6300 4900 +Connection ~ 3950 4900 +Wire Wire Line + 3950 2850 3950 4900 +Connection ~ 2700 4050 +Wire Wire Line + 2700 3300 2700 4050 +Wire Wire Line + 2150 3300 2700 3300 +Connection ~ 3300 4900 +Wire Wire Line + 7450 4900 7450 700 +Connection ~ 3700 4050 +Wire Wire Line + 6050 4050 6050 3150 +Wire Wire Line + 6050 2400 6050 2500 +Wire Wire Line + 3700 1250 3750 1250 +Wire Wire Line + 3700 1400 3700 1250 +Wire Wire Line + 3700 2850 3700 2600 +Connection ~ 2750 4050 +Wire Wire Line + 2750 4050 2750 4150 +Wire Wire Line + 1900 3350 1900 3550 +Wire Wire Line + 1900 2450 1900 1750 +Wire Wire Line + 1900 4050 1900 3650 +Wire Wire Line + 3300 4050 3300 4200 +Wire Wire Line + 3700 3150 3700 4050 +Connection ~ 3300 4050 +Wire Wire Line + 3700 2500 3700 2300 +Wire Wire Line + 6050 1200 6050 1500 +Wire Wire Line + 6400 1200 6050 1200 +Wire Wire Line + 6050 2800 6050 3050 +Wire Wire Line + 2750 4450 2750 4900 +Wire Wire Line + 3300 4500 3300 4900 +Connection ~ 7450 1400 +Wire Wire Line + 2150 4900 2150 3900 +Wire Wire Line + 2150 4900 7450 4900 +Connection ~ 2750 4900 +Wire Wire Line + 4450 2250 3950 2250 +Wire Wire Line + 4450 4050 4450 2250 +Connection ~ 4450 4050 +Wire Wire Line + 6650 2800 6300 2800 +Wire Wire Line + 6650 4050 6650 2800 +Connection ~ 6050 4050 +Wire Wire Line + 1550 900 7250 900 +Wire Wire Line + 1400 4050 6650 4050 +Connection ~ 1900 4050 +Wire Wire Line + 7450 700 4150 700 +Wire Wire Line + 4150 700 4150 1000 +Wire Wire Line + 6850 1450 7350 1450 +Wire Wire Line + 7350 1450 7350 1400 +Wire Wire Line + 7350 1400 7450 1400 +Wire Wire Line + 7250 900 7250 1200 +$Comp +L R R1 +U 1 1 5666A886 +P 2700 4250 +F 0 "R1" H 2750 4380 50 0000 C CNN +F 1 "1" H 2750 4300 50 0000 C CNN +F 2 "" H 2750 4230 30 0000 C CNN +F 3 "" V 2750 4300 30 0000 C CNN + 1 2700 4250 + 0 1 1 0 +$EndComp +$Comp +L D D1 +U 1 1 5666A9A7 +P 3700 3000 +F 0 "D1" H 3700 3100 50 0000 C CNN +F 1 "D" H 3700 2900 50 0000 C CNN +F 2 "" H 3700 3000 60 0000 C CNN +F 3 "" H 3700 3000 60 0000 C CNN + 1 3700 3000 + 0 1 1 0 +$EndComp +$Comp +L D D2 +U 1 1 5666A9E4 +P 6050 2650 +F 0 "D2" H 6050 2750 50 0000 C CNN +F 1 "D" H 6050 2550 50 0000 C CNN +F 2 "" H 6050 2650 60 0000 C CNN +F 3 "" H 6050 2650 60 0000 C CNN + 1 6050 2650 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/triac/triac.cir b/src/SubcircuitLibrary/triac/triac.cir new file mode 100644 index 00000000..c533d42f --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.cir @@ -0,0 +1,23 @@ +* /opt/eSim/src/SubcircuitLibrary/triac/triac.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:32:06 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 8 11 10 PORT +F3 8 9 1 8 10 +v3 7 2 DC +F2 8 9 3 5 10 +v2 6 3 DC +C1 8 9 10u +F1 8 9 4 8 100 +v1 10 4 DC +U1 9 11 6 aswitch +U2 9 2 11 aswitch +R1 8 9 1 +D1 5 8 D +D2 1 7 D + +.end diff --git a/src/SubcircuitLibrary/triac/triac.cir.ckt b/src/SubcircuitLibrary/triac/triac.cir.ckt new file mode 100644 index 00000000..821b417b --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.cir.ckt @@ -0,0 +1,26 @@ +* eeschema netlist version 1.1 (spice format) creation date: 09/20/14 11:23:24
+.include diode.lib
+
+u3 7 4 5 port
+* f3
+d2 3 2 diode
+v3 2 1 dc 0
+* Analog Switch analogswitch
+d1 11 7 diode
+* f2
+v2 8 10 dc 0
+* Analog Switch analogswitch
+c1 7 9 10u
+r1 7 9 1
+* f1
+v1 5 6 dc 0
+Vf3 3 7 0
+f3 7 9 Vf3 10
+Vf2 10 11 0
+f2 7 9 Vf2 10
+Vf1 6 7 0
+f1 7 9 Vf1 100
+a1 9 (1 4) u2
+.model u2 aswitch(cntl_on=-1 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
+a2 9 (4 8) u1
+.model u1 aswitch(cntl_on=1 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/triac/triac.cir.out b/src/SubcircuitLibrary/triac/triac.cir.out new file mode 100644 index 00000000..d2eb7c77 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.cir.out @@ -0,0 +1,38 @@ +* /opt/esim/src/subcircuitlibrary/triac/triac.cir + +.include PowerDiode.lib +* u3 8 11 10 port +* f3 +v3 7 2 dc 0 +* f2 +v2 6 3 dc 0 +c1 8 9 10u +* f1 +v1 10 4 dc 0 +* u1 9 11 6 aswitch +* u2 9 2 11 aswitch +r1 8 9 1 +d1 5 8 PowerDiode +d2 1 7 PowerDiode +Vf3 1 8 0 +f3 8 9 Vf3 10 +Vf2 3 5 0 +f2 8 9 Vf2 10 +Vf1 4 8 0 +f1 8 9 Vf1 100 +a1 9 (11 6) u1 +a2 9 (2 11) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) + +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/triac/triac.cir.out~ b/src/SubcircuitLibrary/triac/triac.cir.out~ new file mode 100644 index 00000000..7bd15a7b --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.cir.out~ @@ -0,0 +1,41 @@ +* /opt/esim/src/subcircuitlibrary/triac/triac.cir + +.include PowerDiode.lib +* u3 8 11 10 port +* f3 +v3 7 2 dc 0 +* f2 +v2 6 3 dc 0 +c1 8 9 10u +* f1 +v1 10 4 dc 0 +* u1 9 11 6 aswitch +* u2 9 2 11 aswitch +r1 8 9 1 +d1 5 8 PowerDiode +d2 1 7 PowerDiode +Vf3 1 8 0 +f3 8 9 Vf3 10 +Vf2 3 5 0 +f2 8 9 Vf2 10 +Vf1 4 8 0 +f1 8 9 Vf1 100 +a1 9 [11 6 ] u1 +a2 9 [2 11 ] u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/triac/triac.pro b/src/SubcircuitLibrary/triac/triac.pro new file mode 100644 index 00000000..5b1f5f89 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.pro @@ -0,0 +1,44 @@ +update=Tue Dec 8 14:16:32 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Sources +LibName7=eSim_Subckt +LibName8=eSim_User +LibName9=power +LibName10=device +LibName11=transistors +LibName12=conn +LibName13=linear +LibName14=regul +LibName15=74xx +LibName16=cmos4000 +LibName17=adc-dac +LibName18=memory +LibName19=xilinx +LibName20=special +LibName21=microcontrollers +LibName22=dsp +LibName23=microchip +LibName24=analog_switches +LibName25=motorola +LibName26=texas +LibName27=intel +LibName28=audio +LibName29=interface +LibName30=digital-audio +LibName31=philips +LibName32=display +LibName33=cypress +LibName34=siliconi +LibName35=opto +LibName36=atmel +LibName37=contrib +LibName38=valves diff --git a/src/SubcircuitLibrary/triac/triac.sch b/src/SubcircuitLibrary/triac/triac.sch new file mode 100644 index 00000000..f30533a0 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.sch @@ -0,0 +1,308 @@ +EESchema Schematic File Version 2 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:triac-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 sep 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U3 +U 3 1 541D1606 +P 1250 1750 +F 0 "U3" H 1250 1700 30 0000 C CNN +F 1 "PORT" H 1250 1750 30 0000 C CNN +F 2 "" H 1250 1750 60 0001 C CNN +F 3 "" H 1250 1750 60 0001 C CNN + 3 1250 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 2 1 541D1601 +P 1300 900 +F 0 "U3" H 1300 850 30 0000 C CNN +F 1 "PORT" H 1300 900 30 0000 C CNN +F 2 "" H 1300 900 60 0001 C CNN +F 3 "" H 1300 900 60 0001 C CNN + 2 1300 900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U3 +U 1 1 541D15F6 +P 1150 4050 +F 0 "U3" H 1150 4000 30 0000 C CNN +F 1 "PORT" H 1150 4050 30 0000 C CNN +F 2 "" H 1150 4050 60 0001 C CNN +F 3 "" H 1150 4050 60 0001 C CNN + 1 1150 4050 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F3 +U 1 1 541D1417 +P 6250 3100 +F 0 "F3" H 6050 3200 50 0000 C CNN +F 1 "10" H 6050 3050 50 0000 C CNN +F 2 "" H 6250 3100 60 0001 C CNN +F 3 "" H 6250 3100 60 0001 C CNN + 1 6250 3100 + 0 1 1 0 +$EndComp +$Comp +L DC v3 +U 1 1 541D13FB +P 6050 1950 +F 0 "v3" H 5850 2050 60 0000 C CNN +F 1 "DC" H 5850 1900 60 0000 C CNN +F 2 "R1" H 5750 1950 60 0000 C CNN +F 3 "" H 6050 1950 60 0001 C CNN + 1 6050 1950 + -1 0 0 1 +$EndComp +$Comp +L CCCS F2 +U 1 1 541D13A3 +P 3900 2550 +F 0 "F2" H 3700 2650 50 0000 C CNN +F 1 "10" H 3700 2500 50 0000 C CNN +F 2 "" H 3900 2550 60 0001 C CNN +F 3 "" H 3900 2550 60 0001 C CNN + 1 3900 2550 + 0 1 1 0 +$EndComp +$Comp +L DC v2 +U 1 1 541D1398 +P 3700 1850 +F 0 "v2" H 3500 1950 60 0000 C CNN +F 1 "DC" H 3500 1800 60 0000 C CNN +F 2 "R1" H 3400 1850 60 0000 C CNN +F 3 "" H 3700 1850 60 0001 C CNN + 1 3700 1850 + 1 0 0 -1 +$EndComp +$Comp +L C C1 +U 1 1 541D137C +P 3300 4350 +F 0 "C1" H 3350 4450 50 0000 L CNN +F 1 "10u" H 3350 4250 50 0000 L CNN +F 2 "" H 3300 4350 60 0001 C CNN +F 3 "" H 3300 4350 60 0001 C CNN + 1 3300 4350 + 1 0 0 -1 +$EndComp +$Comp +L CCCS F1 +U 1 1 541D1363 +P 2100 3600 +F 0 "F1" H 1900 3700 50 0000 C CNN +F 1 "100" H 1900 3550 50 0000 C CNN +F 2 "" H 2100 3600 60 0001 C CNN +F 3 "" H 2100 3600 60 0001 C CNN + 1 2100 3600 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 541D1357 +P 1900 2900 +F 0 "v1" H 1700 3000 60 0000 C CNN +F 1 "DC" H 1700 2850 60 0000 C CNN +F 2 "R1" H 1600 2900 60 0000 C CNN +F 3 "" H 1900 2900 60 0001 C CNN + 1 1900 2900 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 56669B8A +P 4600 1100 +F 0 "U1" H 5050 1400 60 0000 C CNN +F 1 "aswitch" H 5050 1300 60 0000 C CNN +F 2 "" H 5050 1200 60 0000 C CNN +F 3 "" H 5050 1200 60 0000 C CNN + 1 4600 1100 + -1 0 0 1 +$EndComp +$Comp +L aswitch U2 +U 1 1 56669DB5 +P 6400 1350 +F 0 "U2" H 6850 1650 60 0000 C CNN +F 1 "aswitch" H 6850 1550 60 0000 C CNN +F 2 "" H 6850 1450 60 0000 C CNN +F 3 "" H 6850 1450 60 0000 C CNN + 1 6400 1350 + 1 0 0 -1 +$EndComp +Connection ~ 4600 900 +Wire Wire Line + 4600 1250 4600 900 +Wire Wire Line + 1900 1750 1500 1750 +Connection ~ 6300 4900 +Wire Wire Line + 6300 3400 6300 4900 +Connection ~ 3950 4900 +Wire Wire Line + 3950 2850 3950 4900 +Connection ~ 2700 4050 +Wire Wire Line + 2700 3300 2700 4050 +Wire Wire Line + 2150 3300 2700 3300 +Connection ~ 3300 4900 +Wire Wire Line + 7450 4900 7450 700 +Connection ~ 3700 4050 +Wire Wire Line + 6050 4050 6050 3150 +Wire Wire Line + 6050 2400 6050 2500 +Wire Wire Line + 3700 1250 3750 1250 +Wire Wire Line + 3700 1400 3700 1250 +Wire Wire Line + 3700 2850 3700 2600 +Connection ~ 2750 4050 +Wire Wire Line + 2750 4050 2750 4150 +Wire Wire Line + 1900 3350 1900 3550 +Wire Wire Line + 1900 2450 1900 1750 +Wire Wire Line + 1900 4050 1900 3650 +Wire Wire Line + 3300 4050 3300 4200 +Wire Wire Line + 3700 3150 3700 4050 +Connection ~ 3300 4050 +Wire Wire Line + 3700 2500 3700 2300 +Wire Wire Line + 6050 1200 6050 1500 +Wire Wire Line + 6400 1200 6050 1200 +Wire Wire Line + 6050 2800 6050 3050 +Wire Wire Line + 2750 4450 2750 4900 +Wire Wire Line + 3300 4500 3300 4900 +Connection ~ 7450 1400 +Wire Wire Line + 2150 4900 2150 3900 +Wire Wire Line + 2150 4900 7450 4900 +Connection ~ 2750 4900 +Wire Wire Line + 4450 2250 3950 2250 +Wire Wire Line + 4450 4050 4450 2250 +Connection ~ 4450 4050 +Wire Wire Line + 6650 2800 6300 2800 +Wire Wire Line + 6650 4050 6650 2800 +Connection ~ 6050 4050 +Wire Wire Line + 1550 900 7250 900 +Wire Wire Line + 1400 4050 6650 4050 +Connection ~ 1900 4050 +Wire Wire Line + 7450 700 4150 700 +Wire Wire Line + 4150 700 4150 1000 +Wire Wire Line + 6850 1450 7350 1450 +Wire Wire Line + 7350 1450 7350 1400 +Wire Wire Line + 7350 1400 7450 1400 +Wire Wire Line + 7250 900 7250 1200 +$Comp +L R R1 +U 1 1 5666A886 +P 2700 4250 +F 0 "R1" H 2750 4380 50 0000 C CNN +F 1 "1" H 2750 4300 50 0000 C CNN +F 2 "" H 2750 4230 30 0000 C CNN +F 3 "" V 2750 4300 30 0000 C CNN + 1 2700 4250 + 0 1 1 0 +$EndComp +$Comp +L D D1 +U 1 1 5666A9A7 +P 3700 3000 +F 0 "D1" H 3700 3100 50 0000 C CNN +F 1 "D" H 3700 2900 50 0000 C CNN +F 2 "" H 3700 3000 60 0000 C CNN +F 3 "" H 3700 3000 60 0000 C CNN + 1 3700 3000 + 0 1 1 0 +$EndComp +$Comp +L D D2 +U 1 1 5666A9E4 +P 6050 2650 +F 0 "D2" H 6050 2750 50 0000 C CNN +F 1 "D" H 6050 2550 50 0000 C CNN +F 2 "" H 6050 2650 60 0000 C CNN +F 3 "" H 6050 2650 60 0000 C CNN + 1 6050 2650 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/triac/triac.sub b/src/SubcircuitLibrary/triac/triac.sub new file mode 100644 index 00000000..760908b0 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.sub @@ -0,0 +1,32 @@ +* Subcircuit triac +.subckt triac 8 11 10 +* /opt/esim/src/subcircuitlibrary/triac/triac.cir +.include PowerDiode.lib +* f3 +v3 7 2 dc 0 +* f2 +v2 6 3 dc 0 +c1 8 9 10u +* f1 +v1 10 4 dc 0 +* u1 9 11 6 aswitch +* u2 9 2 11 aswitch +r1 8 9 1 +d1 5 8 PowerDiode +d2 1 7 PowerDiode +Vf3 1 8 0 +f3 8 9 Vf3 10 +Vf2 3 5 0 +f2 8 9 Vf2 10 +Vf1 4 8 0 +f1 8 9 Vf1 100 +a1 9 (11 6) u1 +a2 9 (2 11) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) + +* Control Statements + +.ends triac diff --git a/src/SubcircuitLibrary/triac/triac.sub~ b/src/SubcircuitLibrary/triac/triac.sub~ new file mode 100644 index 00000000..ebbed05e --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac.sub~ @@ -0,0 +1,35 @@ +* Subcircuit triac +.subckt triac 8 11 10 +* /opt/esim/src/subcircuitlibrary/triac/triac.cir +.include PowerDiode.lib +* f3 +v3 7 2 dc 0 +* f2 +v2 6 3 dc 0 +c1 8 9 10u +* f1 +v1 10 4 dc 0 +* u1 9 11 6 aswitch +* u2 9 2 11 aswitch +r1 8 9 1 +d1 5 8 PowerDiode +d2 1 7 PowerDiode +Vf3 1 8 0 +f3 8 9 Vf3 10 +Vf2 3 5 0 +f2 8 9 Vf2 10 +Vf1 4 8 0 +f1 8 9 Vf1 100 +a1 9 [11 6 ] u1 +a2 9 [2 11 ] u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 ) +* Control Statements + +.ends triac
\ No newline at end of file diff --git a/src/SubcircuitLibrary/triac/triac_Previous_Values.xml b/src/SubcircuitLibrary/triac/triac_Previous_Values.xml new file mode 100644 index 00000000..80da52b3 --- /dev/null +++ b/src/SubcircuitLibrary/triac/triac_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v2 name="Source type">dc<field1 name="Value">0</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1></source><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">1</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-1</field10></u2></model><devicemodel><d2><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d2><d1><field>/opt/eSim/src/deviceModelLibrary/Diode/PowerDiode.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |